OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MC74VHC540DTR2G

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 5
1 Publication Order Number:
MC74VHC540/D
MC74VHC540
Octal Bus Buffer
Inverting
The MC74VHC540 is an advanced high speed CMOS inverting
octal bus buffer fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The MC74VHC540 features inputs and outputs on opposite sides
of the package and two AND−ed active−low output enables. When
either OE1
or OE2 are high, the terminal outputs are in the high
impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
• High Speed: t
PD
= 3.7 ns (Typ) at V
CC
= 5.0 V
• Low Power Dissipation: I
CC
= 4.0 μA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 1.2 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 124 FETs or 31 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
18
Y1
2
A1
17
Y2
3
A2
16
Y3
4
A3
15
Y4
5
A4
14
Y5
6
A5
13
Y6
7
A6
12
Y7
8
A7
11
Y8
9
A8
OE1
OE2
1
19
OUTPUT
ENABLES
DATA
INPUTS
INVERTING
OUTPUTS
Figure 1. Logic Diagram
SOIC−20
DW SUFFIX
CASE 751D
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
http://onsemi.com
20
MARKING
DIAGRAMS
VHC540
AWLYYWWG
TSSOP−20
DT SUFFIX
CASE 948E
1
1
20
VHC
540
ALYWG
G
L
L
H
X
L
L
X
H
L
H
X
X
FUNCTION TABLE
Inputs
Output Y
OE1 OE2 A
H
L
Z
Z
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
A5
A3
A2
A1
OE1
GND
A8
A7
A6
A4 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Y3
Y2
Y1
OE2
V
CC
Y8
Y7
Y6
Y5
Y4
PIN ASSIGNMENT
MC74VHC540
http://onsemi.com
2
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
CC
DC Supply Voltage – 0.5 to + 7.0 V
V
in
DC Input Voltage – 0.5 to + 7.0 V
V
out
DC Output Voltage – 0.5 to V
CC
+ 0.5 V
I
IK
Input Diode Current − 20 mA
I
OK
Output Diode Current ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 75 mA
P
D
Power Dissipation in Still Air, SOIC Packages†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150 _C
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may adversely
affect device reliability. Functional operation under absolute−maximum−rated conditions is not
implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
in
DC Input Voltage 0 5.5 V
V
out
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature, All Package Types −55 + 125 _C
t
r
, t
f
Input Rise and Fall Time V
CC
= 3.3V ±0.3V
(Figure 1) V
CC
=5.0V ±0.5V
0
0
100
20
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
CC
V
T
A
= 25°C T
A
= − 55 to 125°C
Unit
Min Typ Max Min Max
V
IH
Minimum High−Level
Input Voltage
2.0
3.0 to
5.5
1.50
V
CC
x 0.7
1.50
V
CC
x 0.7
V
V
IL
Maximum Low−Level
Input Voltage
2.0
3.0 to
5.5
0.50
V
CC
x 0.3
0.50
V
CC
x 0.3
V
V
OH
Minimum High−Level
Output Voltage
V
in
= V
IH
or V
IL
I
OH
= − 50μA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
V
V
in
= V
IH
or V
IL
I
OH
= − 4mA
I
OH
= − 8mA
3.0
4.5
2.58
3.94
2.48
3.80
V
OL
Maximum Low−Level
Output Voltage
V
in
= V
IH
or V
IL
I
OL
= 50μA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
I
OL
= 4mA
I
OL
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must be
taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be tied
to an appropriate logic voltage level
(e.g., either GND or V
CC
). Unused
outputs must be left open.
MC74VHC540
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
Symbol Unit
T
A
= − 55 to 125°CT
A
= 25°C
V
CC
V
Test ConditionsParameterSymbol Unit
MaxMinMaxTypMin
V
CC
V
Test ConditionsParameter
I
in
Maximum Input
Leakage Current
V
in
= 5.5V or GND 0 to 5.5 ± 0.1 ± 1.0 μA
I
OZ
Maximum Three−State
Leakage Current
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
5.5 ± 0.25 ± 2.5 μA
I
CC
Maximum Quiescent
Supply Current
V
in
= V
CC
or GND 5.5 4.0 40.0 μA
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0ns)
Symbol Parameter Test Conditions
T
A
= 25°C T
A
= − 55 to 125°C
Unit
Min Typ Max Min Max
t
PLH
,
t
PHL
Maximum Propagation Delay,
A to Y
(Figures 1 and 3)
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
4.8
7.3
7.0
10.5
1.0
1.0
8.5
12.0
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
3.7
5.2
5.0
7.0
1.0
1.0
6.0
8.0
t
PZL
,
t
PZH
Output Enable TIme,
OEn to Y
(Figures 2 and 4)
V
CC
= 3.3 ± 0.3V C
L
= 15pF
R
L
= 1kΩ C
L
= 50pF
6.8
9.3
10.5
14.0
1.0
1.0
12.5
16.0
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
R
L
= 1kΩ C
L
= 50pF
4.7
6.2
7.2
9.2
1.0
1.0
8.5
10.5
t
PLZ
,
t
PHZ
Output Disable Time,
OEn to Y
(Figures 2 and 4)
V
CC
= 3.3 ± 0.3V C
L
= 50pF
R
L
= 1kΩ
11.2 15.4 1.0 17.5 ns
V
CC
= 5.0 ± 0.5V C
L
= 50pF
R
L
= 1kΩ
6.0 8.8 1.0 10.0
t
OSLH
,
t
OSHL
Output to Output Skew V
CC
= 3.3 ± 0.3V C
L
= 50pF
(Note 1)
1.5 ns
V
CC
= 5.0 ± 0.5V C
L
= 50pF
(Note 1)
1.0 ns
C
in
Maximum Input Capacitance 4 10 10 pF
C
out
Maximum Three−State Output
Capacitance (Output in High
Impedance State)
6 pF
C
PD
Power Dissipation Capacitance (Note 2)
Typical @ 25°C, V
CC
= 5.0V
pF
17
1. Parameter guaranteed by design. t
OSLH
= |t
PLHm
− t
PLHn
|, t
OSHL
= |t
PHLm
− t
PHLn
|.
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/ 8 (per bit). C
PD
is used to determine the no−load
dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0ns, C
L
= 50pF, V
CC
= 5.0V)
Symbol Parameter
T
A
= 25°C
Unit
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
0.9 1.2 V
V
OLV
Quiet Output Minimum Dynamic V
OL
− 0.9 − 1.2 V
V
IHD
Minimum High Level Dynamic Input Voltage 3.5 V
V
ILD
Maximum Low Level Dynamic Input Voltage 1.5 V
P1-P3P4-P6P7-P7

MC74VHC540DTR2G

Mfr. #:
Buy MC74VHC540DTR2G
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers 2-5.5V Octal Bus
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet