AD7813YRZ-REEL7 Datasheet AD7813YNZ, AD7813YRUZ, AD7813YRZ | P7-P9

AD7813

–6–

REV. C

CIRCUIT DESCRIPTION

Converter Operation

The AD7813 is a successive approximation analog-to-digital

converter based around a charge redistribution DAC. The ADC

can convert analog input signals in the range 0 V to V

. Fig-

ures 2 and 3 below show simplified schematics of the ADC.

Figure 2 shows the ADC during its acquisition phase. SW2 is

closed and SW1 is in Position A, the comparator is held in a

balanced condition and the sampling capacitor acquires the

signal on V

IN+

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

CLOCK

OSC

COMPARATOR

SW2

ACQUISITION

PHASE

SAMPLING

CAPACITOR

SW1

AGND

Figure 2. ADC Track Phase

When the ADC starts a conversion (see Figure 3), SW2 will

open and SW1 will move to Position B, causing the comparator

to become unbalanced. The Control Logic and the Charge

Redistribution DAC are used to add and subtract fixed amounts

of charge from the sampling capacitor so as to bring the compara-

tor back into a balanced condition. When the comparator is

rebalanced the conversion is complete. The Control Logic gen-

erates the ADC output code. Figure 7 shows the ADC transfer

function.

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

CLOCK

OSC

COMPARATOR

SW2

CONVERSION

PHASE

SAMPLING

CAPACITOR

SW1

AGND

Figure 3. ADC Conversion Phase

TYPICAL CONNECTION DIAGRAM

Figure 4 shows a typical connection diagram for the AD7813. The

parallel interface is implemented using an 8-bit data bus, the

falling edge of CONVST brings the BUSY signal high, and at

the end of conversion the falling edge of BUSY is used to ini-

tiate an Interrupt Service Routine (ISR) on a microprocessor—

see Parallel Interface section for more details. V

REF

is connected

to a well decoupled V

pin to provide an analog input range of

0 V to V

. When V

is first connected the AD7813 powers

up in a low current mode, i.e., power-down. A rising edge on an

internal CONVST input will cause the part to power up—see

Power-Up Times. If power consumption is of concern, the

automatic power-down at the end of a conversion should be

used to improve power performance. See Power vs. Throughput

Rate section of the data sheet.

BUSY

CONVST

DB0-DB7

REF

GND

AD7813



PARALLEL

INTERFACE

0V TO V

REF

INPUT

0.1F10F

SUPPLY

2.7V TO 5.5V

Figure 4. Typical Connection Diagram

Analog Input

Figure 5 shows an equivalent circuit of the analog input struc-

ture of the AD7813. The two diodes, D1 and D2, provide ESD

protection for the analog inputs. Care must be taken to ensure

that the analog input signal never exceeds the supply rails by

more than 200 mV. This will cause these diodes to become

forward biased and start conducting current into the substrate.

The maximum current these diodes can conduct without caus-

ing irreversible damage to the part is 20 mA. The capacitor C2,

in Figure 5, is typically about 4 pF and can be primarily attrib-

uted to pin capacitance. The resistor R1 is a lumped component

made up of the on resistance of a multiplexer and a switch. This

resistor is typically about 125 Ω. The capacitor C1 is the ADC

sampling capacitor and has a capacitance of 3.5 pF.

4pF

125

3.5pF

CONVERT PHASE – SWITCH OPEN

TRACK PHASE – SWITCH CLOSED

Figure 5. Equivalent Analog Input Circuit

DC Acquisition Time

The ADC starts a new acquisition phase at the end of a conver-

sion and ends on the falling edge of the CONVST signal. At the

end of a conversion there is a settling time associated with the

sampling circuit. This settling time lasts approximately 100 ns.

The analog signal on V

is also being acquired during this settling

time; therefore, the minimum acquisition time needed is

approximately 100 ns.

Figure 6 shows the equivalent charging circuit for the sampling

capacitor when the ADC is in its acquisition phase. R2 repre-

sents the source impedance of a buffer amplifier or resistive

network, R1 is an internal multiplexer resistance and C1 is the

sampling capacitor.

125

3.5pF

Figure 6. Equivalent Sampling Circuit

AD7813

–7–

REV. C

During the acquisition phase the sampling capacitor must be

charged to within a 1/2 LSB of its final value. The time it takes

to charge the sampling capacitor (T

CHARGE

) is given by the

following formula:

CHARGE

= 7.6 × (R2 + 125 Ω) × 3.5 pF

For small values of source impedance, the settling time associ-

ated with the sampling circuit (100 ns) is, in effect, the acquisi-

tion time of the ADC. For example, with a source impedance

(R2) of 10 Ω the charge time for the sampling capacitor is

approximately 4 ns. The charge time becomes significant for

source impedances of 2 kΩ and greater.

AC Acquisition Time

In ac applications it is recommended to always buffer analog

input signals. The source impedance of the drive circuitry must

be kept as low as possible to minimize the acquisition time of

the ADC. Large values of source impedance will cause the

THD to degrade at high throughput rates.

ADC TRANSFER FUNCTION

The output coding of the AD7813 is straight binary. The

designed code transitions occur at successive integer LSB values

(i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = V

REF

/1024. The

ideal transfer characteristic for the AD7813 is shown in Figure 7.

000...000

ANALOG INPUT

111...111

000...001

000...010

111...110

111...000

011...111

1LSB

REF

–1LSB

1LSB = V

REF

/1024

ADC CODE

Figure 7. Transfer Characteristic

POWER-UP TIMES

The AD7813 has a 1.5 µs power-up time. When V

is first

connected, the AD7813 is in a low current mode of operation.

In order to carry out a conversion the AD7813 must first be

powered up. The ADC is powered up by a rising edge on an

internally generated CONVST signal, which occurs as a result

of a rising edge on the external CONVST pin. The rising edge

of the external CONVST signal initiates a 1.5 µs pulse on the

internal CONVST signal. This pulse is present to ensure the

part has enough time to power up before a conversion is initi-

ated, as a conversion is initiated on the falling edge of gated

CONVST. See Timing and Control section. Care must be taken

to ensure that the CONVST pin of the AD7813 is logic low

when V

is first applied.

When operating in Mode 2, the ADC is powered down at the

end of each conversion and powered up again before the next

conversion is initiated. (See Figure 8.)

POWER-UP

1.5s

POWER-UP

1.5s

POWER-UP

1.5s

MODE 1

MODE 2

EXT CONVST

INT CONVST

EXT CONVST

INT CONVST

Figure 8. Power-Up Times

POWER VS. THROUGHPUT RATE

By operating the AD7813 in Mode 2, the average power con-

sumption of the AD7813 decreases at lower throughput rates.

Figure 9 shows how the Automatic Power-Down is implemented

using the external CONVST signal to achieve the optimum

power performance for the AD7813. The AD7813 is operated

in Mode 2, and the duration of the external CONVST pulse is

set to be equal to or less than the power-up time of the device.

As the throughput rate is reduced, the device remains in its power-

down state longer and the average power consumption over time

drops accordingly.

EXT CONVST

INT CONVST

POWER-DOWN

POWER-UP

1.5s

CONVERT

2.3s

CYCLE

100s @ 10kSPS

Figure 9. Automatic Power-Down

For example, if the AD7813 is operated in a continuous sam-

pling mode, with a throughput rate of 10 kSPS, the power con-

sumption is calculated as follows. The power dissipation during

normal operation is 10.5 mW, V

= 3 V. If the power-up time

is 1.5 µs and the conversion time is 2.3 µs, the AD7813 can then

be said to dissipate 10.5 mW for 3.8 µs (worst-case) during each

conversion cycle. If the throughput rate is 10 kSPS, the cycle

time is 100 µs and the average power dissipated during each

cycle is (3.8/100) × (10.5 mW) = 400 µW.

AD7813

–8–

REV. C

Typical Performance Characteristics

THROUGHPUT – kSPS

POWER – mW

0.01

0505 1015202530354045

0.1

Figure 10. Power vs. Throughput

–60

–100

dBs

–10

–50

–70

–90

–30

–40

–80

–20

FREQUENCY – kHz

0 17417 35 52 70 87 105 122 140 157

AD7813

2048 POINT FFT

SAMPLING 357.142kHz

30.168kHz

Figure 11. SNR

TIMING AND CONTROL

The AD7813 has only one input for timing and control, i.e.,

the CONVST (convert start signal). The rising edge of this

CONVST signal initiates a 1.5 µs pulse on an internally gener-

ated CONVST signal. This pulse is present to ensure the part

has enough time to power up before a conversion is initiated. If

the external CONVST signal is low, the falling edge of the

internal CONVST signal will cause the sampling circuit to go

into hold mode and initiate a conversion. If, however, the exter-

nal CONVST signal is high when the internal CONVST goes

low, it is upon the falling edge of the external CONVST signal

that the sampling circuitry will go into hold mode and initiate a

conversion. The use of the internally generated 1.5 µs pulse,

as previously described, can be likened to the configuration

shown in Figure 12. The application of a CONVST signal at

the CONVST pin triggers the generation of a 1.5 µs pulse. Both

the external CONVST and this internal CONVST are input to

an OR gate. The resulting signal has the duration of the longer

of the two input signals. Once a conversion has been initiated

the BUSY signal goes high to indicate a conversion is in progress.

At the end of conversion the sampling circuit goes back into its

tracking mode again. The end of conversion is indicated by the

BUSY signal going low. This signal may be used to initiate an

ISR on a microprocessor. At this point the conversion result is

latched into the output register where it may be read. The AD7813

has an 8-bit wide parallel interface. The 10-bit conversion result

is accessed by performing two successive read operations. The

first 8-bit read accesses the 8 MSBs of the conversion result and

the second read accesses the 2 LSBs, as illustrated in Figure 13,

where one performance of the two successive reads is highlighted

after the falling edge of BUSY. The state of the external CONVST

signal at the end of conversion also establishes the mode of opera-

tion of the AD7813.

Mode 1 Operation (High Speed Sampling)

If the external CONVST is logic high when BUSY goes low, the

part is said to be in Mode 1 operation. While operating in Mode

1, the AD7813 will not power down between conversions. The

AD7813 should be operated in Mode 1 for high speed sampling

applications, i.e., throughputs greater than 100 kSPS. Figure 13

shows the timing for Mode 1 operation. From this diagram one

can see that a minimum delay of the sum of the conversion time

and read time must be left between two successive falling edges

of the external CONVST. This is to ensure that a conversion is

not initiated during a read.

Mode 2 Operation (Automatic Power-Down)

At slower throughput rates the AD7813 may be powered down

between conversions to give a superior power performance.

This is Mode 2 Operation and it is achieved by bringing the

CONVST signal logic low before the falling edge of BUSY.

Figure 14, overleaf, shows the timing for Mode 2 Operation.

The falling edge of the external CONVST signal may occur

before or after the falling edge of the internal CONVST signal,

but it is the later occurring falling edge of both that controls

when the first conversion will take place. If the falling edge

of the external CONVST occurs after that of the internal

CONVST, it means that the moment of the first conversion is

controlled exactly, regardless of any jitter associated with the

internal CONVST signal. The parallel interface is still fully

operational while the AD7813 is powered down. The AD7813

is powered up again on the rising edge of the CONVST signal.

The gated CONVST pulse will now remain high long enough

for the AD7813 to fully power up, which takes about 1.5 µs. This

is ensured by the internal CONVST signal, which will remain high

for 1.5 µs.

1.5s

EXT

INT

CONVST

(PIN 4)

GATED

Figure 12.

P1-P3 P4-P6 P7-P9 P10-P12

AD7813YRZ-REEL7

Mfr. #:

Buy AD7813YRZ-REEL7

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 2.7V-5.5V 400kSPS 8-/10-Bit Sampling

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AD7813YRZ-REEL7

AD7813YRZ-REEL7

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