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NL17SHT126P5T5G

P1-P3P4-P5
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 0
1 Publication Order Number:
NL17SHT126/D
NL17SHT126
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The NL17SHT126 is a single gate noninverting 3−state buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The NL17SHT126 requires the 3−state control input (OE) to be set
Low to place the output into the high impedance state.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to
3 V CMOS Logic while operating at the high−voltage power supply.
The NL17SHT126 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the NL17SHT126 to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when
V
CC
= 0 V. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
• High Speed: t
PD
= 3.5 ns (Typ) at V
CC
= 5 V
• Low Power Dissipation: I
CC
= 1 mA (Max) at T
A
= 25°C
• TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2 V
• CMOS−Compatible Outputs: V
OH
> 0.8 V
CC
; V
OL
< 0.1 V
CC
@Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• These are Pb−Free Devices
Figure 1. Pinout (Top View)
IN A
OUT Y
V
CC
OE
IN A
OUT Y
GND
OE
Figure 2. Logic Symbol
1
2
3
4
5
PIN ASSIGNMENT
1
2
3OE
IN A
GND
4
5V
CC
OUT Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
FUNCTION TABLE
L
H
X
A Input Y Output
L
H
Z
OE Input
H
H
L
http://onsemi.com
MARKING
DIAGRAM
SOT−953
CASE 527AE
R = Specific Device Code
M = Month Code
RM
1
NL17SHT126
http://onsemi.com
2
MAXIMUM RATINGS
Symbol Characteristics Value Unit
V
CC
DC Supply Voltage −0.5 to +7.0 V
V
IN
DC Input Voltage −0.5 to +7.0 V
V
OUT
DC Output Voltage −0.5 to V
CC
+ 0.5 V
I
IK
Input Diode Current −20 mA
I
OK
Output Diode Current V
OUT
< GND; V
OUT
> V
CC
±20 mA
I
OUT
DC Output Current ±25 mA
I
CC
DC Supply Current, V
CC
and GND 50 mA
P
D
Power Dissipation in Still Air 50 mW
T
L
Lead Temperature, 1 mm from Case for 10 s 260 °C
T
J
Junction Temperature Under Bias +150 °C
T
stg
Storage Temperature −65 to +150 °C
I
Latchup
Latchup Performance Above V
CC
and Below GND at 125°C (Note 1) ±100 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
V
CC
DC Supply Voltage 3.0 5.5 V
V
IN
DC Input Voltage 0.0 5.5 V
V
OUT
DC Output Voltage 0.0 V
CC
V
T
A
Operating Temperature Range −55 +125 °C
t
r
, t
f
Input Rise and Fall Time V
CC
= 5.0 V ± 0.5 V 0 20 ns/V
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature °C
Time, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100
1000
TIME, YEARS
NORMALIZED FAILURE RATE
T
J
= 80
C°
T
J
= 90
C°
T
J
= 100 C°
T
J
= 110 C°
T
J
= 130 C°
T
J
= 120 C°
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 3. Failure Rate vs. Time Junction Temperature
NL17SHT126
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
CC
(V)
T
A
= 25°C T
A
≤ 85°C −55 ≤ T
A
≤ 125°C
Unit
Min Typ Max Min Max Min Max
V
IH
Minimum High−Level
Input Voltage
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
V
IL
Maximum Low−Level
Input Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
V
OH
Minimum High−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= − 50 mA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
IN
= V
IH
or V
IL
I
OH
= − 4 mA
I
OH
= − 8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
Maximum Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 50 mA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
IN
Maximum Input Leak-
age Current
V
IN
= 5.5 V or GND 0 to
5.5
± 0.1 ± 1.0 ± 1.0
mA
I
CC
Maximum Quiescent
Supply Current
V
IN
= V
CC
or GND 5.5 1.0 20 40
mA
I
CCT
Quiescent Supply
Current
Input: V
IN
= 3.4 V
Other Input: V
CC
or GND
5.5 1.35 1.50 1.65 mA
I
OPD
Output Leakage
Current
V
OUT
= 5.5 V 0.0 0.5 5.0 10
mA
I
OZ
Maximum 3−State
Leakage Current
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
or GND
5.5 ± 0.25 ± 2.5 ± 2.5
mA
AC ELECTRICAL CHARACTERISTICS Input t
r
= t
f
= 3.0 ns
Symbol
Parameter Test Conditions
T
A
= 25°C T
A
≤ 85°C −55 ≤ T
A
≤ 125°C
Unit
Min Typ Max Min Max Min Max
t
PLH
,
t
PHL
Maximum Propagation
Delay, A to Y
(Figures 3 and 5)
V
CC
= 3.3 ± 0.3 V C
L
= 15pF
C
L
= 50pF
5.6
8.1
8.0
11.5
1.0
1.0
9.5
13.0
12.0
16.0
ns
V
CC
= 5.0 ± 0.5 V C
L
= 15pF
C
L
= 50pF
3.8
5.3
5.5
7.5
1.0
1.0
6.5
8.5
8.5
10.5
t
PZL
,
t
PZH
Maximum Output
Enable TIme,OE
to Y
(Figures 4 and 5)
V
CC
= 3.3 ± 0.3 V C
L
= 15pF
R
L
= R
I
= 500 W C
L
= 50pF
5.4
7.9
8.0
11.5
1.0
1.0
9.5
13.0
11.5
15.0
ns
V
CC
= 5.0 ± 0.5 V C
L
= 15pF
R
L
= R
I
= 500 W C
L
= 50pF
3.6
5.1
5.1
7.1
1.0
1.0
6.0
8.0
7.5
9.5
t
PLZ
,
t
PHZ
Maximum Output
Disable Time,OE
to Y
(Figures 4 and 5)
V
CC
= 3.3 ± 0.3 V C
L
= 15pF
R
L
= R
I
= 500 W C
L
= 50pF
6.5
8.0
9.7
13.2
1.0
1.0
11.5
15.0
14.5
18.0
ns
V
CC
= 5.0 ± 0.5 V C
L
= 15pF
R
L
= R
I
= 500 W C
L
= 50pF
4.8
7.0
6.8
8.8
1.0
1.0
8.0
10.0
10.0
12.0
C
in
Maximum Input
Capacitance
4 10 10 10 pF
C
out
Maximum Three−State
Output Capacitance
(Output in High
Impedance State)
6 pF
C
PD
Power Dissipation Capacitance (Note 2)
Typical @ 25°C, V
CC
= 5.0 V
pF
14
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/ 4 (per buffer). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
P1-P3P4-P5

NL17SHT126P5T5G

Mfr. #:
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Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers NON-INVERTING 3- STATE BUF
Lifecycle:
New from this manufacturer.
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