23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
TM
262,144 x 9, 524,288 x 9
NOTE:
1. OE = LOW
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
WCLK
LD
WEN
D
0
- D
7
tLDS
tENS
PAE OFFSET
(LSB)
PAE OFFSET
(MID-BYTE)
t
DS
tDH
tENH
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
4669 drw 17
PAF OFFSET
(MID-BYTE)
PAF OFFSET
(MSB)
tLDH
tCLK
tDH
tCLKH
tCLKL
tLDH
tENH
LD
REN
t
LDH
t
LDH
t
LDS
t
ENS
t
ENH
t
ENH
4669 drw 18
RCLK
Q
0
- Q
7
DATA IN OUTPUT REGISTER
PAE OFFSET
(MSB)
PAF OFFSET
(MSB)
PAE OFFSET
(MID-BYTE)
PAE OFFSET
(LSB)
PAF OFFSET
(MID-BYTE)
PAF OFFSET
(LSB)
t
CLKL
t
CLKH
t
CLK
t
A
t
A
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAF
RCLK
(3)
t
PAF
REN
4669 drw 19
t
ENS
t
ENH
t
ENS
D - (m+1) words in FIFO
(2)
t
PAF
D - m words in FIFO
(2)
t
SKEW2
1
2
12
D-(m+1) words
in FIFO
(2)
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: D = 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111.
In FWFT mode: D = 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111.
3.
t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
PAF
). If the time between the rising edge of
RCLK and the rising edge of WCLK is less than t
SKEW2
, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)