FEATURES
Serial RapidIO Interfaces
•Bandwidthofupto40Gbps
•Lowlatencywithcut-throughcapability
•Individualportpowerdown
•RapidIO Interconnect Specification
(Revision 1.2) compliant
The Tsi564A enhances system scalability through
device configuration and provides architects and
designers with a solution for both throughput
intensive and power sensitive applications.
•PortexibilityformultipleI/O
bandwidthrequirements:
–Uptofour4xmodeportsoreight1x
modeports
–Each4xserialportcanbecongured
astwo1xserialports
•Integratedhigh-speed,full-duplex
SerDeswith8b/10bencoding
•Advancednon-blockinginternal
switchingfabric
–S
pecicallydesignedforlineratetermination
andpreventionofhead-of-lineblocking
–
PortSerDesfrequencycongurationto1.25,
2.5,and3.125Gbits/s
•Look-uptables:Table-basedpacketrouting
Other Device Capabilities
•I
2
CInterface:Supportscongurationthrough
registerinitialization
•HotSwappableports:Enablesuseineld
replaceablebladeapplications
IDT
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THEANALOG
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DIGITALCOMPANY TSI564A
SERIAL RAPIDIO SWITCH PRODUCT BRIEF
Device Overview
The IDT Tsi564A is an industry leading Serial RapidIO switch supporting 40 Gbps aggregate bandwidth. The
Tsi564A is part of a family of switches that enable customers to develop systems with robust features and
high performance at low cost.
The Tsi564A provides designers and architects with maximum scalability to design the device into a
wide range of applications. Flexible port configurations can be selected through multiple port width and
frequency options.
Based on the Serial RapidIO Specification, the Tsi564A incorporates SerDes functionality, error recovery,
priority-based fabric routing, high payload efficiency, and table-based fabric packet routing. In addition,
the Tsi564A supports RapidFabric extensions including data streaming packet switching for interworking
and encapsulation.
The device goes beyond standard specification requirements to solve system level issues by optimizing
performance, lowering power consumption, and supporting hot swappable I/Os. The extensive buffering
and traffic management architecture is specifically designed for line rate termination and the prevention of
head-of-line blocking.
Typical Applications
The Tsi564A can be used in many embedded communication applications. It provides chip-to-chip interconnect
between I/O devices and can replace existing proprietary backplane fabrics for board-to-board interconnect
which improves system cost and product time-to-market.
The Tsi564A provides traffic aggregation through packet prioritization when it is used with RapidIO-enabled
I/O devices. When it is in a system with multiple RapidIO-enabled processors it provides high performance
peer-to-peer communication through its non-blocking switch fabric.
Integrated Device Technology
Integrated Device Technology
1
Tsi564A
™
Serial RapidIO Switch
Internal
Switching Fabric
Registers
I
2
C JTAG
®
SP0
(4x or 1x)
SP1
(1x only)
SP4
(4x or 1x)
SP5
(1x only)
SP2
(4x or 1x)
SP3
(1x only)
SP6
(4x or 1x)
SP7
(1x only)
or
Up to 4 Serial RapidIO Ports - 1x Mode
Up to 2 Serial RapidIO Ports - 1x/4x Mode
or
Up to 4 Serial RapidIO Ports - 1x Mode
Up to 2 Serial RapidIO Ports - 1x/4x Mode
Slave
Devices
IEEE1149.1
Boundary Scan
POWER MANAGEMENT
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INTERFACE & CONNECTIVITY
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CLOCKS & TIMING
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MEMORY & LOGIC
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TOUCH & USER INTERFACE
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VIDEO & DISPLAY
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AUDIO