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PCA9633DP2,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
PCA9633_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 25 July 2008 13 of 43
NXP Semiconductors
PCA9633
4-bit Fm+ I
2
C-bus LED driver
[1] See Section 7.7 “Using the PCA9633 with and without external drivers” for more details. Normal LEDs can be driven directly in either
mode. Some newer LEDs include integrated Zener diodes to limit voltage transients, reduce EMI and protect the LEDs, and these must
be driven only in the open-drain mode to prevent overheating the IC.
[2] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9633. Applicable to registers from
02h (PWM0) to 08h (LEDOUT) only.
[3] See Section 7.4 “Active LOW output enable input” for more details.
[4] OUTNE[1:0] is only for PCA9633 16-pin version.
7.3.3 PWM registers 0 to 3, PWMx — Individual brightness control registers
A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through
256 linear steps from 00h (0 % duty cycle = LED output off) to FFh
(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs
programmed with LDRx = 10 or 11 (LEDOUT register).
(1)
7.3.4 Group duty cycle control, GRPPWM
When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency
signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is
then used as a global brightness control allowing the LED outputs to be dimmed with the
same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 4 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
1 to 0 OUTNE[1:0]
[3][4]
R/W 00 When OE = 1 (output drivers not enabled), LEDn = 0.
01* When
OE = 1 (output drivers not enabled):
LEDn = 1 when OUTDRV = 1
LEDn = high-impedance when OUTDRV = 0 (same as OUTNE[1:0] = 10)
10 When
OE = 1 (output drivers not enabled), LEDn = high-impedance.
11 reserved
Table 9. MODE2 - Mode register 2 (address 01h) bit description
…continued
Legend: * default value.
Bit Symbol Access Value Description
Table 10. PWM0 to PWM3 - PWM registers 0 to 3 (address 02h to 05h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
02h PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle
03h PWM1 7:0 IDC1[7:0] R/W 0000 0000* PWM1 Individual Duty Cycle
04h PWM2 7:0 IDC2[7:0] R/W 0000 0000* PWM2 Individual Duty Cycle
05h PWM3 7:0 IDC3[7:0] R/W 0000 0000* PWM3 Individual Duty Cycle
duty cycle
IDC 7:0[]
256
------------------------
=
Table 11. GRPPWM - Group duty cycle control register (address 06h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
06h GRPPWM 7:0 GDC[7:0] R/W 1111 1111 GRPPWM register
PCA9633_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 25 July 2008 14 of 43
NXP Semiconductors
PCA9633
4-bit Fm+ I
2
C-bus LED driver
When DMBLNK bit is programmed with 1, GRPPWM and GRPFREQ registers define a
global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to
10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
(2)
7.3.5 Group frequency, GRPFREQ
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73 s).
(3)
7.3.6 LED driver output state, LEDOUT
LDRx = 00 — LED driver x is off (default power-up state).
LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking
not controlled).
LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx
register.
LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be
controlled through its PWMx register and the GRPPWM registers.
duty cycle
GDC 7:0[]
256
---------------------------
=
Table 12. GRPFREQ - Group Frequency register (address 07h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
07h GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register
global blinking period
GFRQ 7:0[]1+
24
----------------------------------------
in ondssec()=
Table 13. LEDOUT - LED driver output state register (address 08h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
08h LEDOUT 7:6 LDR3 R/W 00* LED3 output state control
5:4 LDR2 R/W 00* LED2 output state control
3:2 LDR1 R/W 00* LED1 output state control
1:0 LDR0 R/W 00* LED0 output state control
PCA9633_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 25 July 2008 15 of 43
NXP Semiconductors
PCA9633
4-bit Fm+ I
2
C-bus LED driver
7.3.7 I
2
C-bus subaddress 1 to 3, SUBADRx
Subaddresses are programmable through the I
2
C-bus. Default power-up values are E2h,
E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up
(the corresponding SUBx bit in MODE1 register is equal to 0).
Once subaddresses have been programmed to their right values, SUBx bits need to be
set to 1 in order to have the device acknowledging these addresses (MODE1 register).
Only the 7 MSBs representing the I
2
C-bus subaddress are valid. The LSB in SUBADRx
register is a read-only bit (0).
When SUBx is set to 1, the corresponding I
2
C-bus subaddress can be used during either
an I
2
C-bus read or write sequence.
7.3.8 LED All Call I
2
C-bus address, ALLCALLADR
The LED All Call I
2
C-bus address allows all the PCA9633s in the bus to be programmed
at the same time (ALLCALL bit in register MODE1 must be equal to 1, power-up default
state). This address is programmable through the I
2
C-bus and can be used during either
an I
2
C-bus read or write sequence. The register address can be programmed as a
sub call.
Only the 7 MSBs representing the All Call I
2
C-bus address are valid. The LSB in
ALLCALLADR register is a Read-only bit (0).
If ALLCALL bit = 0, the device does not acknowledge the address programmed in register
ALLCALLADR.
Table 14. SUBADR1 to SUBADR3 - I
2
C-bus subaddress registers 0 to 3 (address 09h to
0Bh) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
09h SUBADR1 7:1 A1[7:1] R/W 1110 001* I
2
C-bus subaddress 1
0 A1[0] R only 0* reserved
0Ah SUBADR2 7:1 A2[7:1] R/W 1110 010* I
2
C-bus subaddress 2
0 A2[0] R only 0* reserved
0Bh SUBADR3 7:1 A3[7:1] R/W 1110 100* I
2
C-bus subaddress 3
0 A3[0] R only 0* reserved
Table 15. ALLCALLADR - LED All Call I
2
C-bus address register (address 0Ch) bit
description
Legend: * default value.
Address Register Bit Symbol Access Value Description
0Ch ALLCALLADR 7:1 AC[7:1] R/W 1110 000* ALLCALL I
2
C-bus
address register
0 AC[0] R only 0* reserved
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43

PCA9633DP2,118

Mfr. #:
Buy PCA9633DP2,118
Manufacturer:
NXP Semiconductors
Description:
LED Lighting Drivers 4BIT I2C FM+ TP LED CON RST OE
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New from this manufacturer.
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