OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LTC3406AIS5#TRMPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LTC3406A
10
3406afa
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses in LTC3406A circuits: V
IN
quiescent current
and I
2
R losses. The V
IN
quiescent current loss dominates
the effi ciency loss at very low load currents whereas the
I
2
R loss dominates the effi ciency loss at medium to high
load currents. In a typical effi ciency plot, the effi ciency
curve at very low load currents can be misleading since
the actual power lost is of no consequence as illustrated
in Figure 2.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current fl owing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current.
Other losses including C
IN
and C
OUT
ESR dissipative losses
and inductor core losses generally account for less than
2% total additional loss.
Thermal Considerations
In most applications the LTC3406A does not dissipate
much heat due to its high effi ciency. But, in applications
where the LTC3406A is running at high ambient tem-
perature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.
To avoid the LTC3406A from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
APPLICATIONS INFORMATION
Figure 2. Power Lost vs Load Current
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical charac-
teristics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate
is switched from high to low to high again, a packet of
charge, dQ, moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger
than the DC bias current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of
the internal top and bottom switches. Both the DC bias
and gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
OUTPUT CURRENT (mA)
0.001
POWER LOSS (W)
0.01
0.1
1
0.1 10 100 1000
3406A F02
0.0001
1
V
OUT
= 1.2V
V
OUT
= 1.8V
V
OUT
= 2.5V
V
IN
= 3.6V
LTC3406A
11
3406afa
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3406A in dropout at an
input voltage of 2.7V, a load current of 600mA and an
ambient temperature of 70°C. From the typical perfor-
mance graph of switch resistance, the R
DS(ON)
of the
P-channel switch at 70°C is approximately 0.27Ω. There-
fore, power dissipated by the part is:
P
D
= I
LOAD
2
• R
DS(ON)
= 97.2mW
For the SOT-23 package, the θ
JA
is 250°C/W. Thus, the
junction temperature of the regulator is:
T
J
= 70°C + (0.0972)(250) = 94.3°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction temperature
is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (
∆
I
LOAD
• ESR), where ESR is the effective series
resistance of C
OUT
.
∆
I
LOAD
also begins to charge or dis-
charge C
OUT
, which generates a feedback error signal. The
regulator loop then acts to return V
OUT
to its steady-state
value. During this recovery time V
OUT
can be monitored
for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in paral-
lel with C
OUT
, causing a rapid drop in V
OUT
. No regulator
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive
so that the load rise time is limited to approximately
(25 • C
LOAD
). Thus, a 10μF capacitor charging to 3.3V
would require a 250μs rise time, limiting the charging
current to about 130mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3406A. These items are also illustrated graphically in
Figures 3 and 4. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace, the V
OUT
trace and the V
IN
trace should be kept
short, direct and wide.
2. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be
connected between the (+) plate of C
OUT
and ground.
3. Does C
IN
connect to V
IN
as closely as possible? This
capacitor provides the AC current to the internal power
MOSFETs.
4. Keep the switching node, SW, away from the sensitive
V
FB
node.
5. Keep the (–) plates of C
IN
and C
OUT
, and the IC ground,
as close as possible.
APPLICATIONS INFORMATION
LTC3406A
12
3406afa
Design Example
As a design example, assume the LTC3406A is used
in a single lithium-ion battery-powered cellular phone
application. The V
IN
will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.6A but most of the time it will be in
standby mode, requiring only 2mA. Effi ciency at both
low and high load currents is important. Output voltage
is 2.5V. With this information we can calculate L using
Equation (1),
L =
1
f
()
I
L
( )
V
OUT
1
V
OUT
V
IN
(3)
Substituting V
OUT
= 2.5V, V
IN
= 4.2V,
∆
I
L
= 240mA and
f = 1.5MHz in Equation (3) gives:
L =
2.5V
1.5MHz(240mA)
1
2.5V
4.2V
= 2.81μH
A 2.2μH inductor works well for this application. For best
effi ciency choose a 720mA or greater inductor with less
than 0.2Ω series resistance.
C
IN
will require an RMS current rating of at least 0.3A ≅
I
LOAD(MAX)
/2 at temperature and C
OUT
will require an ESR
of less than 0.25Ω. In most cases, a ceramic capacitor
will satisfy this requirement.
Figure 3. LTC3406A Layout Diagram
Figure 4. LTC3406A Suggested Layout
APPLICATIONS INFORMATION
RUN
LTC3406A
GND
SW
L1
R2 R1
C
FWD
BOLD LINES INDICATE HIGH CURRENT PATHS
V
IN
V
OUT
3406A F03
4
5
1
3
+
–
2
V
FB
V
IN
C
IN
C
OUT
LTC3406A
GND
3406A F04
PIN 1
V
OUT
V
IN
VIA TO V
OUT
SW
C
OUT
C
IN
L1
R2
C
FWD
R1
VIA TO V
IN
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LTC3406AIS5#TRMPBF

Mfr. #:
Buy LTC3406AIS5#TRMPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1.5MHz, 600mA Sync Buck Reg in SOT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet