SIT2025BI-S3-28E-125.000000G

SiT2025B
High Frequency, Automotive AEC-Q100 SOT23 Oscillator
Rev. 1.5
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Performance Plots
[8]
4.5
4.7
4.9
5.1
5.3
5.5
5.7
5.9
6.1
6.3
6.5
115 117 119 121 123 125 127 129 131 133 135 137
1.8 2.5 2.8 3.0 3.3
Idd (mA)
Frequency (MHz)
Figure 7. Idd vs Frequency
-25
-20
-15
-10
-5
0
5
10
15
20
25
-55 -35 -15 5 25 45 65 85 105 125
DUT1 DUT2 DUT3 DUT4
DUT5 DUT6
DUT7
DUT8 DUT9 DUT10 DUT11 DUT12 DUT13 DUT14
DUT15 DUT16 DUT17 DUT18 DUT19 DUT20
Frequency (ppm)
Temperature (°C)
Figure 8. Frequency vs Temperature
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
115 117 119 121 123 125 127 129 131 133 135 137
1.8 V 2.5 V 2.8 V 3.0 V 3.3 V
RMS period jitter (ps)
Frequency (MHz)
Figure 9. RMS Period Jitter vs Frequency
45
46
47
48
49
50
51
52
53
54
55
115 117 119 121 123 125 127 129 131 133 135 137
1.8 V 2.5 V 2.8 V 3.0 V 3.3 V
Duty cycle (%)
Frequency
(MHz)
Figure 10. Duty Cycle vs Frequency
0.0
0.5
1.0
1.5
2.0
2.5
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120
1.8 V 2.5 V 2.8 V 3.0 V 3.3 V
Rise time (ns)
Temperature (°C)
Figure 11. 20%-80% Rise Time vs Temperature
0.0
0.5
1.0
1.5
2.0
2.5
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120
1.8 V 2.5 V 2.8 V 3.0 V 3.3 V
Fall time (ns)
Temperature (°C)
Figure 12. 20%-80% Fall Time vs Temperature
SiT2025B
High Frequency, Automotive AEC-Q100 SOT23 Oscillator
Rev. 1.5
Page 5 of 15
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Performance Plots
[8]
1.0
1.2
1.4
1.6
1.8
2.0
115 117 119 121 123 125 127 129 131 133 135 137
1.8 V 2.5 V 2.8 V 3.0 V 3.3 V
IPJ (ps)
Frequency (MHz)
Figure 13. RMS Integrated Phase Jitter Random
(12 kHz to 20 MHz) vs Frequency
[9]
0.4
0.5
0.6
0.7
0.8
0.9
1.0
115 117 119 121 123 125 127 129 131 133 135 137
1.8 V 2.5 V 2.8 V
3.0 V
3.3 V
IPJ (ps)
Frequency (MHz)
Figure 14. RMS Integrated Phase Jitter Random
(900 kHz to 20 MHz) vs Frequency
[9]
Notes:
8. All plots are measured with 15 pF load at room temperature, unless otherwise stated.
9. Phase noise plots are measured with Agilent E5052B signal source analyzer.
Rev. 1.5
Page 6 of 15
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SiT2025B High Frequency, Automotive AEC-Q100 SOT23 Oscillator
Programmable Drive Strength
The SiT2025 includes a programmable drive strength feature
to provide a simple, flexible tool to optimize the clock rise/fall
time for specific applications. Benefits from the program-
mable drive strength feature are:
Improves system radiated electromagnetic interference
(EMI) by slowing down the clock rise/fall time.
Improves the downstream clock receiver’s (RX) jitter
by decreasing (speeding up) the clock rise/fall time.
Ability to drive large capacitive loads while maintaining
full swing with sharp edge rates.
For more detailed information about rise/fall time control and
drive strength selection, see the SiTime Application Notes
section: http://www.sitime.com/support/application-notes.
EMI Reduction by Slowing Rise/Fall Time
Figure 15 shows the harmonic power reduction as the
rise/fall times are increased (slowed down). The rise/fall
times are expressed as a ratio of the clock period. For the
ratio of 0.05, the signal is very close to a square wave. For
the ratio of 0.45, the rise/fall times are very close to near-
triangular waveform. These results, for example, show that
the 11th clock harmonic can be reduced by 35 dB if the
rise/fall edge is increased from 5% of the period to 45% of
the period.
Figure 15. Harmonic EMI reduction as a Function
of Slower Rise/Fall Time
Jitter Reduction with Faster Rise/Fall Time
Power supply noise can be a source of jitter for the down-
stream chipset. One way to reduce this jitter is to speed up
the rise/fall time of the input clock. Some chipsets may also
require faster rise/fall time in order to reduce their sensitivi-
ty to this type of jitter. Refer to the Rise/Fall Time Tables
(Table 7 to Table 11) to determine the proper drive strength.
High Output Load Capability
The rise/fall time of the input clock varies as a function of the
actual capacitive load the clock drives. At any given drive
strength, the rise/fall time becomes slower as the output load
increases. As an example, for a 3.3V SiT2025 device with
default drive strength setting, the typical rise/fall time is
0.46ns for 5 pF output load. The typical rise/fall time slows
down to 1 ns when the output load increases to 15 pF. One
can choose to speed up the rise/fall time to 0.72 ns by then
increasing the driven strength setting on the SiT2025 to “F”.
The SiT2025 can support up to 30 pF in maximum capacitive
loads with up to 3 additional drive strength settings. Refer to
the Rise/Tall Time Tables (Table 7 to 11
) to determine the
proper drive strength for the desired combination of output
load vs. rise/fall time.
SiT2025 Drive Strength Selection
Tables 7 through 11 define the rise/fall time for a given
capacitive load and supply voltage.
1.
Select the table that matches the SiT2025 nominal
supply voltage (1.8V, 2.5V, 2.8V, 3.0V, 3.3V).
2.
Select the capacitive load column that matches the
application requirement (5 pF to 30 pF)
3.
Under the capacitive load column, select the de-
sired rise/fall times.
4.
The left-most column represents the part number
code for the corresponding drive strength.
5.
Add the drive strength code to the part number for
ordering purposes.
Calculating Maximum Frequency
Based on the rise and fall time data given in Tables 7
through 11, the maximum frequency the oscillator can op-
erate with guaranteed full swing of the output voltage over
temperature as follows:
=
1
5 x Trf_20/80
Max Frequency
where Trf_20/80 is the typical value for 20%-80% rise/fall
time.
Example 1
Calculate f
MAX
for the following condition:
Vdd = 3.3V (Table 11)
Capacitive Load: 30 pF
Desired Tr/f time = 1.31 ns (rise/fall time part number
code = F)
Part number for the above example:
SiT2024BAES2-18E-66.666660
Drive strength code is inserted here. Default setting is “-”

SIT2025BI-S3-28E-125.000000G

Mfr. #:
Manufacturer:
Description:
MEMS OSC XO 125.0000MHZ LVCMOS
Lifecycle:
New from this manufacturer.
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