OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

CBT3125DB,112

P1-P3P4-P6P7-P9P10-P11
Philips Semiconductors Product data
CBT3125Quadruple FET bus switch
2001 Dec 12
3
LOGIC DIAGRAM
1B
2B
3B
4B
3
6
8
11
2
5
9
12
1A
2A
3A
4A
1
4
10
13
1OE
2OE
3OE
4OE
SA00564
Pin numbers shown are for 14-pin package-types.
Figure 3. CBT3125 logic diagram (positive logic)
FUNCTION TABLE (each bus switch)
INPUT
OE
FUNCTION
L A = B
H disconnect
ABSOLUTE MAXIMUM RATINGS
1
Over operating free-air temperature range, unless otherwise noted.
SYMBOL
PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
supply voltage range –0.5 7 V
V
I
input voltage range see Note 2 –0.5 7 V
continuous channel current — 128 mA
I
K
input clamp current V
I/O
< 0 — –50 mA
T
stg
storage temperature range –65 +150 °C
NOTES:
1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
1
SYMBOL
PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
supply voltage 4.5 5.5 V
V
IH
high-level control input voltage 2 — V
V
IL
low-level control input voltage — 0.8 V
T
amb
operating ambient temperature in free-air –40 +85 °C
NOTE:
1. All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation.
Philips Semiconductors Product data
CBT3125Quadruple FET bus switch
2001 Dec 12
4
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range, unless otherwise noted.
SYMBOL
PARAMETER CONDITIONS MIN. TYP.
1
MAX. UNIT
V
IK
Input clamp voltage
V
CC
= 4.5 V;
I
I
= –18 mA
— — –1.2 V
I
I
Input leakage current
V
CC
= 5.5 V;
V
I
= 5.5 V or GND
— — ±1 µA
I
CC
Quiescent supply current
V
CC
= 5.5 V; I
O
= 0;
V
I
= V
CC
or GND
— — 3 µA
∆I
CC
Additional supply current per
input pin (Note 2)
control inputs
V
CC
= 5.5 V;
one input at 3.4 V,
other inputs at V
CC
or GND
— — 2.5 mA
C
I
Input capacitance control inputs V
I
= 3 V or 0 — 1.7 — pF
C
IO(OFF)
Power-off leakage current V
O
= 3 V or 0; OE = V
CC
— 3.4 — pF
V
P
Pass gate voltage V
CC
= 5.0 V; V
I
= 5.0 V — 3.8 — V
V
CC
= 4.5 V; V
I
= 0 V;
I
I
= 64 mA
— 5 7 Ω
r
on
On-resistance (Note 3)
V
CC
= 4.5 V; V
I
= 0 V;
I
I
= 30 mA
— 5 7 Ω
V
CC
= 4.5 V; V
I
= 2.4 V;
I
I
= –15 mA
— 10 15 Ω
NOTES:
1. All typical values are at V
CC
= 5 V, unless otherwise noted. T
amb
= 25 °C.
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
AC CHARACTERISTICS
T
amb
= –40 to +85 °C; C
L
= 50 pF, unless otherwise noted.
SYMBOL
PARAMETER
FROM TO
V
CC
= 5 V ± 0.5 V
UNIT
SYMBOL
PARAMETER
(INPUT) (OUTPUT)
Min Max
UNIT
t
pd
Propagation delay
1
A or B B or A — 0.25 ns
t
en
Output enable time
to High and Low level
OE A or B 1.0 5.4 ns
t
dis
Output disable time
from High and Low level
OE A or B 1 4.7 ns
NOTE:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
Philips Semiconductors Product data
CBT3125Quadruple FET bus switch
2001 Dec 12
5
AC WAVEFORMS
V
M
= 1.5 V, V
IN
= GND to 3.0V
INPUT
1.5 V
OUTPUT
t
PLH
t
PHL
SA00028
1.5 V
1.5 V 1.5 V
3 V
0 V
V
OH
V
OL
t
PLH
and t
PHL
are the same as t
pd
.
Waveform 1. Input to Output Propagation Delays
Output Control
1.5 V
t
PZH
t
PHZ
V
OH
V
OL
t
PZL
t
PLZ
3.5 V
0 V
V
OL
+ 0.3 V
V
OH
– 0.3 V
SA00558
1.5 V
1.5 V 1.5 V
0 V
3 V
Output
Waveform 1
S1 at 7 V
(see Note)
Note:
Waveform 1 is for an output with internal conditions such that
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is high except when disabled by the output control.
Output
Waveform 2
S1 at Open
(see Note)
t
PLZ
and t
PHZ
are the same as t
dis
.
t
PZL
and t
PZH
are the same as t
en
.
Waveform 2. Output Enable and Disable Times
TEST CIRCUIT
C
L
= 50 pF
500 Ω
Load Circuit
DEFINITIONS
C
L
= Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
TEST S1
t
pd
open
t
PLZ
/t
PZL
7 V
t
PHZ
/t
PZH
open
SA00012
500 Ω
From Output
Under Test
S1
7 V
Open
GND
t
PLZ
and t
PHZ
are the same as t
dis
.
t
PZL
and t
PZH
are the same as t
en
.
NOTES:
1. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
≤ 2.5 ns,
t
f
≤ 2.5 ns.
2. The outputs are measured one at a time with one transition per
measurement.
P1-P3P4-P6P7-P9P10-P11

CBT3125DB,112

Mfr. #:
Buy CBT3125DB,112
Manufacturer:
Nexperia
Description:
Digital Bus Switch ICs QUAD FET BUS SWITCH
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet