XC2C32A CoolRunner-II CPLD
DS310 (v2.1) November 6, 2008 www.xilinx.com 5
Product Specification
Schmitt Trigger Input DC Voltage Specifications
AC Electrical Characteristics Over Recommended Operating Conditions
Symbol Parameter Test Conditions Min. Max. Units
V
CCIO
Input source voltage 1.4 3.9 V
V
T+
Input hysteresis threshold voltage 0.5 x V
CCIO
0.8 x V
CCIO
V
V
T-
0.2 x V
CCIO
0.5 x V
CCIO
V
Symbol Parameter
-4 -6
UnitsMin. Max. Min. Max.
T
PD1
Propagation delay single p-term - 3.8 - 5.5 ns
T
PD2
Propagation delay OR array - 4.0 - 6.0 ns
T
SUD
Direct input register clock setup time 1.7 - 2.2 - ns
T
SU1
Setup time fast (single p-term) 1.9 - 2.6 - ns
T
SU2
Setup time (OR array) 2.1 - 3.1 - ns
T
HD
Direct input register hold time 0.0 - 0.0 - ns
T
H
P-term hold time 0.0 - 0.0 - ns
T
CO
Clock to output - 3.7 - 4.7 ns
F
TOGGLE
(1)
Internal toggle rate - 500 - 300 MHz
F
SYSTEM1
(2)
Maximum system frequency - 323 - 200 MHz
F
SYSTEM2
(2)
Maximum system frequency - 303 - 182 MHz
F
EXT1
(3)
Maximum external frequency - 179 - 137 MHz
F
EXT2
(3)
Maximum external frequency - 172 - 128 MHz
T
PSUD
Direct input register p-term clock setup time 0.4 - 0.9 - ns
T
PSU1
P-term clock setup time (single p-term) 0.6 - 1.3 - ns
T
PSU2
P-term clock setup time (OR array) 0.8 - 1.8 - ns
T
PHD
Direct input register p-term clock hold time 1.5 - 1.6 - ns
T
PH
P-term clock hold 1.3 - 1.2 - ns
T
PCO
P-term clock to output - 5.0 - 6.0 ns
T
OE
/T
OD
Global OE to output enable/disable - 4.7 - 5.5 ns
T
POE
/T
POD
P-term OE to output enable/disable - 6.2 - 6.7 ns
T
MOE
/T
MOD
Macrocell driven OE to output enable/disable - 6.2 - 6.9 ns
T
PAO
P-term set/reset to output valid - 5.5 - 6.8 ns
T
AO
Global set/reset to output valid - 4.5 - 5.5 ns
T
SUEC
Register clock enable setup time 2.0 - 3.0 - ns
T
HEC
Register clock enable hold time 0.0 - 0.0 - ns
T
CW
Global clock pulse width High or Low 1.4 - 2.2 - ns
T
PCW
P-term pulse width High or Low 4.0 - 6.0 - ns
T
APRPW
Asynchronous preset/reset pulse width (High or Low) 4.0 - 6.0 - ns
T
CONFIG
(4)
Configuration time - 50 - 50 μs
Notes:
1. F
TOGGLE
is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet).
2. F
SYSTEM1
(1/T
CYCLE
) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per
macrocell while F
SYSTEM2
is through the OR array.
3. F
EXT1
(1/T
SU1
+T
CO
) is the maximum external frequency using one p-term while F
EXT2
is through the OR array.
4. Typical configuration current during T
CONFIG
is 500 μA.
