OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

XC2C32A-6VQG44C

P1-P3P4-P6P7-P9P10-P12P13-P14
DS310 (v2.1) November 6, 2008 www.xilinx.com 1
Product Specification
© 2004–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• Optimized for 1.8V systems
- As fast as 3.8 ns pin-to-pin logic delays
- As low as 12 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation: 1.5V through 3.3V
• Available in multiple package options
- 32-land QFN with 21 user I/Os
- 44-pin VQFP with 33 user I/Os
- 56-ball CP BGA with 33 user I/Os
- Pb-free available for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
- Optional DualEDGE triggered registers
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED
drive
- Optional configurable grounds on unused I/Os
- Optional bus-hold, 3-state, or weak pullup on
selected I/O pins
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
- PLA architecture
· Superior pinout retention
· 100% product term routability across function
block
- Hot pluggable
Refer to the CoolRunner™-II family data sheet for the archi-
tecture description.
Description
The CoolRunner™-II 32-macrocell device is designed for
both high performance and low power applications. This
lends power savings to high-end communication equipment
and high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved.
This device consists of two Function Blocks interconnected
by a low power Advanced Interconnect Matrix (AIM). The
AIM feeds 40 true and complement inputs to each Function
Block. The Function Blocks consist of a 40 by 56 P-term
PLA and 16 macrocells which contain numerous configura-
tion bits that allow for combinational or registered modes of
operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain, and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers can be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a
synchronous clock source. Macrocell registers can be indi-
vidually configured to power up to the zero or one state. A
global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset, and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
The CoolRunner-II 32-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see Table 1 ). This device is also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II 32A
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
0
XC2C32A CoolRunner-II CPLD
DS310 (v2.1) November 6, 2008
00
Product Specification
R
XC2C32A CoolRunner-II CPLD
2 www.xilinx.com DS310 (v2.1) November 6, 2008
Product Specification
R
RealDigital Design Technology
Xilinx® CoolRunner-II CPLDs are fabricated on a
0.18 micron process technology which is derived from lead-
ing edge FPGA product development. CoolRunner-II
CPLDs employ RealDigital, a design technique that makes
use of CMOS technology in both the fabrication and design
methodology. RealDigital design technology employs a cas-
cade of CMOS gates to implement sum of products instead
of traditional sense amplifier methodology. Due to this tech-
nology, Xilinx CoolRunner-II CPLDs achieve both high per-
formance and low power operation.
Supported I/O Standards
The CoolRunner-II CPLD 32 macrocell features both
LVCMOS and LVTTL I/O implementations. See Table 1 for
I/O standard voltages. The LVTTL I/O standard is a general
purpose EIA/JEDEC standard for 3.3V applications that use
an LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, and 1.8V applica-
tions. CoolRunner-II CPLDs are also 1.5V I/O compatible
with the use of Schmitt-trigger inputs.
Table 1 : I/O Standards for XC2C32A
IOSTANDARD
Attribute
Output
V
CCIO
Input
V
CCIO
Input
V
REF
Board
Termination
Voltage V
T
LVTTL 3.3 3.3 N/A N/A
LVCMOS33 3.3 3.3 N/A N/A
LVCMOS25 2.5 2.5 N/A N/A
LVCMOS18 1.8 1.8 N/A N/A
LVCM OS15
(1)
1.5 1.5 N/A N/A
1. LVCMOS15 requires Schmitt-trigger inputs.
Figure 1: I
CC
vs. Frequency
Tabl e 2 : I
CC
vs. Frequency (LVCMOS 1.8V T
A
= 25°C)
(1)
Frequency (MHz)
0 25 50 75 100 150 175 200 225 250 300
Typical I
CC
(mA) 0.016 0.87 1.75 2.61 3.44 5.16 5.99 6.81 7.63 8.36 9.93
Notes:
1. 16-bit up/down, resettable binary counter (one counter per function block).
Frequency (MHz)
DS091_01_030105
I
CC
(mA)
0
0
5
10
15
20
30025020015010050
XC2C32A CoolRunner-II CPLD
DS310 (v2.1) November 6, 2008 www.xilinx.com 3
Product Specification
R
Recommended Operating Conditions
DC Electrical Characteristics Over Recommended Operating Conditions
Absolute Maximum Ratings
Symbol Description Value Units
V
CC
Supply voltage relative to ground –0.5 to 2.0 V
V
CCIO
Supply voltage for output drivers –0.5 to 4.0 V
V
JTAG
(2)
JTAG input voltage limits –0.5 to 4.0 V
V
CCAUX
JTAG input supply voltage –0.5 to 4.0 V
V
IN
(1)
Input voltage relative to ground –0.5 to 4.0 V
V
TS
(1)
Voltage applied to 3-state output –0.5 to 4.0 V
T
STG
(3)
Storage Temperature (ambient) –65 to +150 °C
T
J
Junction Temperature +150 °C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins might undershoot to –2.0V or overshoot to +4.5V, provided this overshoot or undershoot lasts less than 10 ns and
with the forcing current being limited to 200 mA.
2. Valid over commercial temperature range.
3. For soldering guidelines and thermal considerations, see the Device Packaging
information on the Xilinx website. For Pb free
packages, see XAPP427.
Symbol Parameter Min Max Units
V
CC
Supply voltage for internal logic
and input buffers
Commercial T
A
= 0°C to +70°C 1.7 1.9 V
Industrial T
A
= –40°C to +85°C 1.7 1.9 V
V
CCIO
Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V
Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V
Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V
Supply voltage for output drivers @ 1.5V operation 1.4 1.6 V
V
CCAUX
JTAG programming pins 1.7 3.6 V
Symbol Parameter Test Conditions Typical Max. Units
I
CCSB
Standby current Commercial V
CC
= 1.9V, V
CCIO
= 3.6V 22 90 μA
I
CCSB
Standby current Industrial V
CC
= 1.9V, V
CCIO
= 3.6V 38 150 μA
I
CC
(1)
Dynamic current f = 1 MHz - 0.25 mA
f = 50 MHz - 2.5 mA
C
JTAG
JTAG input capacitance f = 1 MHz - 10 pF
C
CLK
Global clock input capacitance f = 1 MHz - 12 pF
C
IO
I/O capacitance f = 1 MHz - 10 pF
I
IL
(2)
Input leakage current V
IN
= 0V or V
CCIO
to 3.9V - +/-1 μA
I
IH
(2)
I/O High-Z leakage V
IN
= 0V or V
CCIO
to 3.9V - +/-1 μA
Notes:
1. 16-bit up/down resettable binary counter (one per Function Block) tested at
V
CC
= V
CCIO
= 1.9V.
2. See Quality and Reliability section of the CoolRunner-II family data sheet.
P1-P3P4-P6P7-P9P10-P12P13-P14

XC2C32A-6VQG44C

Mfr. #:
Buy XC2C32A-6VQG44C
Manufacturer:
Xilinx
Description:
CPLD - Complex Programmable Logic Devices XC2C32A-6VQG44C
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet