MAX6884ETP+ Datasheet MAX6884ETP+, MAX6885ETP+, MAX6884ETP+T | P25-P27

Configuring the MAX6884/MAX6885

The MAX6884/MAX6885 factory-default configuration

sets all registers to 00h except for bits R91h[0],

R92h[0], R93h[0], R94h[0], R95h[0], which are set to 1.

This configuration sets all three programmable outputs

(RESET, UV/OV, WDO) as open drain, and RESET and

UV/OV dependent on MR (putting all outputs into high-

impedance states until the device is reconfigured by

the user). Each device requires configuration before full

power is applied to the system. Below is a general

step-by-step procedure for programming the

MAX6884/MAX6885:

1) Apply a supply voltage to IN1–IN4 or V

, depend-

ing on the programmed configuration (see the

Powering the MAX6884/MAX6885 section). The

applied voltage must be 2.7V or higher.

2) Transmit data through the serial interface. Write to

the configuration registers first to ensure the device

is configured properly (see the Write Byte and

Block Write sections).

3) Use the read word protocol to read back the data from

the configuration registers to verify the data was writ-

ten (see the Receive Byte and Block Read sections).

4) Write the same data written to the configuration reg-

isters to the appropriate configuration EEPROM reg-

isters. After completing EEPROM configuration,

apply full power to the system to begin normal oper-

ation. The nonvolatile EEPROM stores the configura-

tion information while power is off.

Software Reboot

A software reboot restores the EEPROM configuration

to the volatile registers without cycling the power sup-

plies. Use the send byte command with data byte C4h

to initiate a software reboot. The 2.5ms (max) power-up

delay also applies after a software reboot.

MAX6884/MAX6885

EEPROM-Programmable, Hex

Power-Supply Supervisory Circuits

______________________________________________________________________________________ 25

Table 12. Register Map (continued)

ADDRESS

EEPROM

MEMORY

ADDRESS

READ/

WRITE

DESCRIPTION

25h — R ADC Conversion Data for AUXIN (2 LSBs) (Table 3)

26h — R ADC Conversion Data for V

(8 MSBs) (Table 3)

27h — R ADC Conversion Data for V

(2 LSBs) (Table 3)

28h — R Fault Flags for Primary Voltage Detectors (Table 9)

29h — R Fault Flags for Secondary Voltage Detectors (Table 9)

2Ah — R Fault Flags for RESET, UV/OV, and WDO (Table 9)

CONFIGURATION

EEPROM USER EEPROM

CONFIGURATION

DATA

(R/W)

ADC AND FAULT

REGISTERS

(READ ONLY)

00h

17h

80h 40h

7Fh

97h

18h

2Ah

Figure 5. Memory Map

SMBus/I

C-Compatible Serial Interface

The MAX6884/MAX6885 feature an I

C/SMBus-compati-

ble 2-wire serial interface consisting of a serial data line

(SDA) and a serial clock line (SCL). SDA and SCL facili-

tate bidirectional communication between the

MAX6884/MAX6885 and the master device at clock

rates up to 400kHz. Figure 6 shows the 2-wire interface

timing diagram. The MAX6884/MAX6885 are transmit/

receive slave-only devices, relying upon a master

device to generate a clock signal. The master device

(typically a microcontroller) initiates data transfer on the

bus and generates SCL to permit that transfer.

A master device communicates to the MAX6884/

MAX6885 by transmitting the proper address followed by

command and/or data words. Each transmit sequence is

framed by a START (S) or REPEATED START (SR) condi-

tion and a STOP (P) condition. Each word transmitted

over the bus is 8 bits long and is always followed by an

acknowledge pulse.

SCL is a logic input, while SDA is an open-drain

input/output. SCL and SDA both require external pullup

resistors to generate the logic-high voltage. Use 4.7kΩ

resistors for most applications.

Bit Transfer

Each clock pulse transfers one data bit. The data on

SDA must remain stable while SCL is high (see Figure

7), otherwise the MAX6884/MAX6885 register a START

or STOP condition (see Figure 8) from the master. SDA

and SCL idle high when the bus is not busy.

MAX6884/MAX6885

EEPROM-Programmable, Hex

Power-Supply Supervisory Circuits

26 ______________________________________________________________________________________

STOP

CONDITION

REPEATED START

CONDITION

START

CONDITION

HIGH

LOW

SU:DAT

SU:STA

SU:STO

HD:STA

BUF

HD:STA

HD:DAT

SCL

SDA

START

CONDITION

Figure 6. Serial Interface Timing

DATA LINE STABLE,

DATA VALID

SDA

SCL

CHANGE OF

DATA ALLOWED

Figure 7. Bit Transfer

START

CONDITION

SDA

SCL

STOP

CONDITION

Figure 8. Start and Stop Conditions

MAX6884/MAX6885

EEPROM-Programmable, Hex

Power-Supply Supervisory Circuits

______________________________________________________________________________________ 27

SCL

SDA BY

TRANSMITTER

SDA BY

RECEIVER

START

CONDITION

CLOCK PULSE FOR ACKNOWLEDGE

Figure 9. Acknowledge

Start and Stop Conditions

Both SCL and SDA idle high when the bus is not busy. A

master device signals the beginning of a transmission

with a START (S) condition (see Figure 8) by transitioning

SDA from high to low while SCL is high. The master

device issues a STOP (P) condition (see Figure 8) by

transitioning SDA from low to high while SCL is high. A

STOP condition frees the bus for another transmission.

The bus remains active if a REPEATED START condition

is generated, such as in the block read protocol (see

Figure 11).

Early STOP Conditions

The MAX6884/MAX6885 recognize a STOP condition at

any point during transmission except if a STOP condition

occurs in the same high pulse as a START condition.

This condition is not a legal I

C format; at least one clock

pulse must separate any START and STOP condition.

Repeated START Conditions

A REPEATED START (SR) condition may indicate a

change of data direction on the bus. Such a change

occurs when a command word is required to initiate a

read operation (see Figure 11). SR may also be used

when the bus master is writing to several I

C devices

and does not want to relinquish control of the bus. The

MAX6884/MAX6885 serial interface supports continu-

ous write operations with or without an SR condition

separating them. Continuous read operations require

SR conditions because of the change in direction of

data flow.

Acknowledge

The acknowledge bit (ACK) is the 9th bit attached to any

8-bit data word. The receiving device always generates

an ACK. The MAX6884/MAX6885 generate an ACK

when receiving an address or data by pulling SDA low

during the 9th clock period (see Figure 9). When trans-

mitting data, such as when the master device reads data

back from the MAX6884/MAX6885, the MAX6884/

MAX6885 wait for the master device to generate an ACK.

Monitoring ACK allows for detection of unsuccessful

data transfers. An unsuccessful data transfer occurs if

the receiving device is busy or if a system fault has

occurred. In the event of an unsuccessful data transfer,

the bus master should reattempt communication at a

later time. The MAX6884/MAX6885 generate a NACK

after the command byte during a software reboot, while

writing to the EEPROM, or when receiving an illegal

memory address.

Slave Address

The MAX6884/MAX6885 slave address conforms to the

following table:

SA7

(MSB)

SA6

SA5

SA4

SA3

SA2

SA1

SA0

(LSB)

10100

R/W

X = Don’t care.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P34

MAX6884ETP+

Mfr. #:

Buy MAX6884ETP+

Manufacturer:

Maxim Integrated

Description:

Supervisory Circuits EEPROM-Prog Hex Power-Sup Sequencer

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MAX6884ETP+

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