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MC100EL51DT

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 8
1 Publication Order Number:
MC10EL51/D
MC10EL51, MC100EL51
5V ECL Differential Clock
D Flip‐Flop
Description
The MC10EL/100EL51 is a differential clock D flip-flop with reset.
The device is functionally similar to the E151 device with higher
performance capabilities. With propagation delays and output
transition times significantly faster than the E151 the EL51 is ideally
suited for those applications which require the ultimate in AC
performance.
The reset input is an asynchronous, level triggered signal. Data
enters the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition
of the clock. The differential clock inputs of the EL51 allow the device
to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability
under open input (pulled down to V
EE
) conditions.
The 100 Series contains temperature compensation.
Features
• 475 ps Propagation Delay
• 2.8 GHz Toggle Frequency
• ESD Protection:
♦ > 1 kV Human Body Model
♦ > 100 V Machine Model
• PECL Mode Operating Range:
♦ V
CC
= 4.2 V to 5.7 V with V
EE
= 0 V
• NECL Mode Operating Range:
♦ V
CC
= 0 V with V
EE
= −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on D, R, and CLK
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity:
♦ Level 1 for SOIC−8NB
♦ Level 3 for TSSOP−8
♦ For Additional Information, see Application Note AND8003/D
• Flammability Rating:
♦ UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34
• Transistor Count = 73 devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
MARKING DIAGRAMS*
KL51
ALYWG
G
SOIC−8NB
D SUFFIX
CASE 751−07
1
8
TSSOP−8
DT SUFFIX
CASE 948R−02
1
8
1
8
www.onsemi.com
KEL51
ALYW
G
1
8
HL51
ALYWG
G
1
8
HEL51
ALYW
G
1
8
(Note: Microdot may be in either location)
H = MC10
K = MC100
4X = MC10
2M= MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M
= Date Code
G = Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D
.
ORDERING INFORMATION
Device Package Shipping
†
MC10EL51DG SOIC−8
(Pb-Free)
98 Units/Tube
MC10EL51DR2G SOIC−8
(Pb-Free)
2500/Tape & Reel
TSSOP−8
(Pb-Free)
MC100EL51DG 98 Units/Tube
SOIC−8
(Pb-Free)
MC10EL51DTG 100 Units/Tube
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
.
MC10EL51, MC100EL51
www.onsemi.com
2
1
2
3
45
6
7
8
Q
V
EE
V
CC
Figure 1. Logic Diagram and Pinout Assignment
D
Q
CLK
CLK
R
D
R
Table 1. TRUTH TABLE
D*
L
H
X
R*
L
L
H
CLK*
Z
Z
X
Q**
L
H
L
Z = LOW to HIGH Transition
R ECL Reset Input
D ECL Data Input
CLK, CLK
ECL Clock Inputs
Q, Q
ECL Data Outputs
V
CC
Positive Supply
V
EE
Negative Supply
Table 2. PIN DESCRIPTION
* Pin will default low when left open.
**Pin will default low when inputs are left open.
PIN FUNCTION
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 8 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −8 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
≤ V
CC
V
I
≥ V
EE
6
−6
V
I
out
Output Current Continuous
Surge
50
100
mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8NB 190
130
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board SOIC−8NB 41 to 44 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
TSSOP−8 185
140
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W
T
sol
Wave Solder (Pb-Free) <2 to 3 sec @ 260°C 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
MC10EL51, MC100EL51
www.onsemi.com
3
Table 4. 10EL SERIES PECL DC CHARACTERISTICS (V
CC
= 5.0 V; V
EE
= 0 V (Note 1))
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 24 29 24 29 24 29 mA
V
OH
Output HIGH Voltage (Note 2) 3920 4010 4110 4020 4105 4190 4090 4185 4280 mV
V
OL
Output LOW Voltage (Note 2) 3050 3200 3350 3050 3210 3370 3050 3227 3405 mV
V
IH
Input HIGH Voltage (Single-Ended) 3770 4110 3870 4190 3940 4280 mV
V
IL
Input LOW Voltage (Single-Ended) 3050 3500 3050 3520 3050 3555 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
2.5 4.6 2.5 4.6 2.5 4.6 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.3
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.25 V / −0.5 V.
2. Outputs are terminated through a 50 W resistor to V
CC
− 2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1 V.
Table 5. 10EL SERIES NECL DC CHARACTERISTICS (V
CC
= 0 V; V
EE
= −5.0 V (Note 1))
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 24 29 24 29 24 29 mA
V
OH
Output HIGH Voltage (Note 2) −1080 −990 −890 −980 −895 −810 −910 −815 −720 mV
V
OL
Output LOW Voltage (Note 2) −1950 −1800 −1650 −1950 −1790 −1630 −1950 −1773 −1595 mV
V
IH
Input HIGH Voltage (Single-Ended) −1230 −890 −1130 −810 −1060 −720 mV
V
IL
Input LOW Voltage (Single-Ended) −1950 −1500 −1950 −1480 −1950 −1445 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
−2.5 −0.4 −2.5 −0.4 −2.5 −0.4 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.3
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.25 V / −0.5 V.
2. Outputs are terminated through a 50 W resistor to V
CC
− 2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1 V.
P1-P3P4-P6P7-P7

MC100EL51DT

Mfr. #:
Buy MC100EL51DT
Manufacturer:
ON Semiconductor
Description:
Flip Flops 5V ECL Diff Clock
Lifecycle:
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