OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADUM1445ARQZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
Rev. E | Page 13 of 25
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 19.
Parameter Rating
Supply Voltages (V
DD1
, V
DD2
) −0.5 V to +5 V
Input Voltages (V
IA
, V
IB
) −0.5 V to V
DDI
+ 0.5 V
Output Voltages (V
OA
, V
OB
) −0.5 V to V
DD2
+ 0.5 V
Average Output Current per Pin
1
Side 1 (I
O1
) −10 mA to +10 mA
Side 2 (I
O2
) −10 mA to +10 mA
Common-Mode Transients
2
−100 kV/µs to +100 kV/µs
Storage Temperature (T
ST
) Range −65°C to +150°C
Ambient Operating Temperature
(T
A
) Range
−40°C to +125°C
1
See Figure 4 for maximum safety power values for various temperatures.
2
Refers to common-mode transients across the insulation barrier. Common-mode
transients exceeding the absolute maximum ratings can cause latch-up or
permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 20. Maximum Continuous Working Voltage
1
Parameter Value Constraint
AC Voltage
60 Hz Bipolar Waveform 565 V
PEAK
50-year minimum lifetime
60 Hz Unipolar Waveform
Basic Insulation
975 V
PEAK
50-year minimum lifetime
DC Voltage
Basic Insulation 975 V
PEAK
50-year minimum lifetime
1
Refers to continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more details.
ESD CAUTION
Table 21. Truth Table (Positive Logic) for all Models
V
Ix
Input
1, 2
V
DDI
State
3
V
DDO
State
4
EN
x
Input
1
V
Ox
Output
1
Description
H Powered Powered L H Normal operation; data is high and refresh is enabled.
L Powered Powered L L Normal operation; data is low and refresh is enabled.
H Powered Powered H H Output is high, and refresh is disabled.
L Powered Powered H L
5
Output is low, and refresh is disabled.
L Unpowered Powered L Default Input unpowered. Outputs are in the default state, high for
ADuM1440, ADuM1441, and ADuM1442, and low ADuM1445,
ADuM1446, and ADuM1447. Outputs return to input state
within 150 µs of V
DDI
power restoration. See the pin function
descriptions (Table 22 through Table 24) for more details.
L Unpowered Powered H Hold Input unpowered. Outputs are the last state before input
power is shut down.
X Powered Unpowered X Z Output unpowered. Output pins are in high impedance state.
Outputs return to input state within 34 µs of V
DDO
power
restoration. See the pin function descriptions (Table 22 through
Table 24) for more details.
1
H = high, L = low, X = don’t care, and Z = high impedance.
2
V
Ix
and V
Ox
refer to the input and output signals of a given channel (A, B, C, or D).
3
V
DDI
refers to the power supply on the input side of a given channel (A, B, C, or D).
4
V
DDO
refers to the power supply on the output side of a given channel (A, B, C, or D).
5
Low input must follow a falling edge; otherwise, it can be in the default low state.
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
Rev. E | Page 14 of 25
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD1
1
GND
1
1
2
V
IA
3
V
IB
4
V
DD2
16
GND
2
2
15
V
OA
14
V
OB
13
V
IC
5
V
OC
12
V
ID
6
V
OD
11
EN
1
7
EN
2
10
GND
1
1
8
GND
2
2
9
ADuM1440/
ADuM1445
TOP VIEW
(Not to Scale)
1
PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND
1
IS RECOMMENDED.
2
PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING
BOTH TO GND
2
IS RECOMMENDED.
11845-004
Figure 5. ADuM1440/ADuM1445 QSOP Pin Configuration
V
DD1
1
GND
1
1
2
V
IA
3
V
IB
4
V
DD2
NIC = NOT INTERNALLY CONNECTED.
20
GND
2
2
19
V
OA
18
V
OB
17
V
IC
5
V
OC
16
V
ID
6
V
OD
15
EN
1
7
EN
2
14
NIC
8
NIC
13
NIC
9
NIC
12
GND
1
1
10
GND
2
2
11
ADuM1440/
ADuM1445
TOP VIEW
(Not to Scale)
11845-104
1
PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED.
CONNECTING BOTH TO GND
1
IS RECOMMENDED.
2
PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED.
CONNECTING BOTH TO GND
2
IS RECOMMENDED.
Figure 6. ADuM1440/ADuM1445 SSOP Pin Configuration
Table 22. ADuM1440/ADuM1445 Pin Function Descriptions
1
QSOP
Pin No.
2
SSOP
Pin No.
Mnemonic Description
1 1 V
DD1
Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01
µF to 0.1 µF range between V
DD1
(Pin 1) and GND
1
(Pin 2).
2, 8 2, 10 GND
1
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting
both to GND
1
is recommended.
3 3 V
IA
Logic Input A.
4 4 V
IB
Logic Input B.
5 5 V
IC
Logic Input C.
6 3 V
ID
Logic Input D.
7 7 EN
1
Refresh/Watchdog Enable 1. Connecting Pin 7 to GND
1
enables input/output refresh and
watchdog functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to V
DD1
disables refresh and watchdog functionality for lowest power operation, see the Applications
Information section for a detailed description of this mode. EN
1
and EN
2
must be set to the same
logic state.
9, 15 11, 19 GND
2
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and
connecting both to GND
2
is recommended.
10 14 EN
2
Refresh/Watchdog Enable 2. Connecting Pin 10 to GND
2
enables input/output refresh and
watchdog functionality for Side 2, supporting standard iCoupler operation. Tying Pin 10 to V
DD2
disables refresh and watchdog functionality for lowest power operation, see the Applications
Information section for a detailed description of this mode. EN
1
and EN
2
must be set to the same
logic state.
11
15
V
OD
Logic Output D.
12 16 V
OC
Logic Output C.
13 17 V
OB
Logic Output B.
14 18 V
OA
Logic Output A.
16 20 V
DD2
Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01
µF to 0.1 µF range between V
DD2
(Pin 16) and GND
2
(Pin 15).
N/A 8, 9, 12, 13 NC No Connect. Do not connect to this pin.
1
Reference the AN-1109 Application Note for specific layout guidelines.
2
N/A = not applicable.
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
Rev. E | Page 15 of 25
V
DD1
1
GND
1
1
2
V
IA
3
V
IB
4
V
DD2
16
GND
2
2
15
V
OA
14
V
OB
13
V
IC
5
V
OC
12
V
OD
6
V
ID
11
EN
1
7
EN
2
10
GND
1
1
8
GND
2
2
9
ADuM1441/
ADuM1446
TOP VIEW
(Not to Scale)
1
PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND
1
IS RECOMMENDED.
2
PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING
BOTH TO GND
2
IS RECOMMENDED.
1
1845-005
Figure 7. ADuM1441/ADuM1446 QSOP Pin Configuration
V
DD1
1
GND
1
1
2
V
IA
3
V
IB
4
V
DD2
NIC = NOT INTERNALLY CONNECTED.
20
GND
2
2
19
V
OA
18
V
OB
17
V
IC
5
V
OC
16
V
OD
6
V
ID
15
EN
1
7
EN
2
14
NIC
8
NIC
13
NIC
9
NIC
12
GND
1
1
10
GND
2
2
11
ADuM1441/
ADuM1446
TOP VIEW
(Not to Scale)
1
PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED.
CONNECTING BOTH TO GND
1
IS RECOMMENDED.
2
PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED.
CONNECTING BOTH TO GND
2
IS RECOMMENDED.
11845-108
Figure 8. ADuM1441/ADuM1446 SSOP Pin Configuration
Table 23. ADuM1441/ADuM1446 Pin Function Descriptions
1
QSOP
Pin No.
2
SSOP
Pin No. Mnemonic Description
1 1 V
DD1
Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01
µF to 0.1 µF range between V
DD1
(Pin 1) and GND
1
(Pin 2).
2, 8 2, 10 GND
1
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting
both to GND
1
is recommended.
3 3 V
IA
Logic Input A.
4 4 V
IB
Logic Input B.
5 5 V
IC
Logic Input C.
6 3 V
OD
Logic Output D.
7 7 EN
1
Refresh/Watchdog Enable 1. Connecting Pin 7 to GND
1
enables input/output refresh and
watchdog functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to V
DD1
disables refresh and watchdog functionality for lowest power operation, see the Applications
Information section for a detailed description of this mode. EN
1
and EN
2
must be set to the same
logic state.
9, 15 11, 19 GND
2
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and
connecting both to GND
2
is recommended.
10 14 EN
2
Refresh/Watchdog Enable 2. Connecting Pin 10 to GND
2
enables input/output refresh and
watchdog functionality for Side 2, supporting standard iCoupler operation. Tying Pin 10 to V
DD2
disables refresh and watchdog functionality for lowest power operation, see the Applications
Information section for a detailed description of this mode. EN
1
and EN
2
must be set to the same
logic state.
11 15 V
ID
Logic Input D.
12 16 V
OC
Logic Output C.
13 17 V
OB
Logic Output B.
14 18 V
OA
Logic Output A.
16 20 V
DD2
Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01
µF to 0.1 µF range between V
DD2
(Pin 16) and GND
2
(Pin 15).
N/A 8, 9, 12, 13 NC No Connect. Do not connect to this pin.
1
Reference the AN-1109 Application Note for specific layout guidelines.
2
N/A = not applicable.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

ADUM1445ARQZ

Mfr. #:
Buy ADUM1445ARQZ
Manufacturer:
Analog Devices Inc.
Description:
Digital Isolators Micro-power Quad-CH Digital Isolator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet