7
AT49BV1604A(T)/1614A(T)
1411F–FLASH–03/02
128-BIT PROTECTION REGISTER: The AT49BV/LV16X4A(T) contains a 128-bit register that
can be used for security purposes in system design. The protection register is divided into two
64-bit blocks. The two blocks are designated as block A and block B. The data in block A is
non-changeable and is programmed at the factory with a unique number. The data in block B
is programmed by the user and can be locked out such that data in the block cannot be repro-
grammed. To program block B in the protection register, the four-bus cycle Program
Protection Register command must be used as shown in the Command Definition table on
page 8. To lock out block B, the four-bus cycle Lock Protection Register command must be
used as shown in the Command Definition table. Data bit D1 must be zero during the fourth
bus cycle. All other data bits during the fourth bus cycle are don’t cares. Please see the “Pro-
tection Register Addressing Table” on page 9 for the address locations in the protection
register. To read the protection register, the Product ID Entry command is given followed by a
normal read operation from an address within the protection register. After reading the protec-
tion register, the Product ID Exit command must be given prior to performing any other
operation.
DATA
POLLING: The AT49BV/LV16X4A(T) features Data Polling to indicate the end of a pro-
gram cycle. During a program cycle an attempted read of the last byte/word loaded will result
in the complement of the loaded data on I/O7. Once the program cycle has been completed,
true data is valid on all outputs and the next cycle may begin. During a chip or sector erase
operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device. Data
Polling may begin at any
time during the program cycle. Please see “Status Bit Table” on page 21 for more details.
TOGGLE BIT: In addition to Data
Polling, the AT49BV/LV16X4A(T) provides another method
for determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the same memory plane will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling and
valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2, which can be used in conjunction with the toggle
bit that is available on I/O6. While a sector is erase suspended, a read or a program operation
from the suspended sector will result in the I/O2 bit toggling. Please see “Status Bit Table” on
page 21 for more details.
RDY/BUSY
: For the AT49BV/LV1614A(T), an open-drain Ready/Busy output pin provides
another method of detecting the end of a program or erase operation. RDY/BUSY
is actively
pulled low during the internal program and erase cycles and is released at the completion of
the cycle. The open-drain connection allows for OR-tying of several devices to the same
RDY/BUSY
line.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against
inadvertent programs to the AT49BV/LV16X4A(T) in the following ways: (a) V
CC
sense: if V
CC
is below 1.8V (typical), the program function is inhibited. (b) V
CC
power-on delay: once V
CC
has reached the V
CC
sense level, the device will automatically time out 10 ms (typical) before
programming. (c) Program inhibit: holding any one of OE
low, CE high or WE high inhibits pro-
gram cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE
or CE inputs will not
initiate a program cycle.
INPUT LEVELS: While operating with a 2.65V to 3.3V power supply, the address inputs and
control inputs (OE
,CEand WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to V
CC
+0.6V.
OUTPUT LEVELS: For the AT49BV1604A(T), output high levels (V
OH
) are equal to V
CCQ
-
0.2V (not V
CC
). For 2.65V - 3.3V output levels, V
CCQ
must be tied to V
CC
. For 1.8V - 2.2V out-
put levels, V
CCQ
must be regulated to 2.0V ± 10%, while V
CC
must be regulated to 2.65V - 3.0V
(for minimum power).
