OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

PCA9531PW,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
PCA9531_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 19 February 2009 10 of 27
NXP Semiconductors
PCA9531
8-bit I
2
C-bus LED dimmer
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 9. System configuration
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I
2
C-BUS
MULTIPLEXER
SLAVE
Fig 10. Acknowledgement on the I
2
C-bus
002aaa987
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
PCA9531_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 19 February 2009 11 of 27
NXP Semiconductors
PCA9531
8-bit I
2
C-bus LED dimmer
7.4 Bus transactions
Fig 11. Write to register
0 AS
slave address
START condition R/W acknowledge
from slave
002aac507
0 0 AI 0 B2B1B00
command byte
A
acknowledge
from slave
12345678SCL 9
SDA DATA 1 A
write to register
data out from port
t
v(Q)
acknowledge
from slave
DATA 1 VALID
data to register
1 0 0 A2 A1 A01
Fig 12. Read from register
1 0 0 A2 A1 A0 0 AS1
START condition R/W
acknowledge
from slave
002aac508
A
acknowledge
from slave
SDA
A P
acknowledge
from master
data from register
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
1 A
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
data from register
DATA (last byte)
command byte
0 0 AI 0 B2 B10B0
Auto-Increment
register address
if AI = 1
1 0 0 A2 A1 A01
Remark: This figure assumes the command byte has previously been programmed with 00h.
Fig 13. Read Input port register
1 0 0 A2 A1 A0 1 AS1
START condition R/W acknowledge
from slave
002aac509
A
acknowledge
from master
SDA NA
read from
port
data into
port
P
t
h(D)
data from port
no acknowledge
from master
data from port
DATA 4
slave address
DATA 1
STOP
condition
DATA 2 DATA 3 DATA 4
t
su(D)
PCA9531_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 19 February 2009 12 of 27
NXP Semiconductors
PCA9531
8-bit I
2
C-bus LED dimmer
8. Application design-in information
8.1 Minimizing I
DD
when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to V
DD
through a
resistor as shown in Figure 14. Since the LED acts as a diode, when the LED is off the
I/O V
I
is about 1.2 V less than V
DD
. The supply current, I
DD
, increases as V
I
becomes
lower than V
DD
and is specified as ∆I
DD
in Table 12 “Static characteristics”.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater than or equal to V
DD
when the LED is off.
Figure 15 shows a high value resistor in parallel with the LED. Figure 16 shows V
DD
less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O V
I
at or above V
DD
and prevents additional supply current consumption when the LED is off.
LED0 to LED5 are used as LED drivers.
LED6 and LED7 are used as regular GPIOs.
Fig 14. Typical application
PCA9531
LED0
LED1
SDA
SCL
RESET
3.3 V
I
2
C-BUS/SMBus
MASTER
002aac523
SDA
SCL
V
DD
A2
A1
A0
V
SS
5 V
10 kΩ
LED2
LED3
LED4
LED5
LED6
LED7
GPIOs
10 kΩ10 kΩ
Fig 15. High value resistor in parallel with
the LED
Fig 16. Device supplied by a lower voltage
002aac189
LED
V
DD
LEDn
100 kΩ
V
DD
002aac190
LED
V
DD
LEDn
3.3 V 5 V
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

PCA9531PW,118

Mfr. #:
Buy PCA9531PW,118
Manufacturer:
NXP Semiconductors
Description:
LED Lighting Drivers 8-BIT I2C FM OD LED DIM RST
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet