© Semiconductor Components Industries, LLC, 2008
December, 2008 − Rev. 9
1 Publication Order Number:
MMUN2111LT1/D
MMUN2111LT1 Series
Preferred Devices
Bias Resistor Transistors
PNP Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base-emitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the SOT-23
package which is designed for low power surface mount applications.
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• The SOT-23 package can be soldered using wave or reflow. The
modified gull-winged leads absorb thermal stress during soldering
eliminating the possibility of damage to the die.
• Available in 8 mm embossed tape and reel.
• Pb−Free Packages are Available
MAXIMUM RATINGS (T
A
= 25°C unless otherwise noted)
Rating
Symbol Value Unit
Collector-Base Voltage V
CBO
50 Vdc
Collector-Emitter Voltage V
CEO
50 Vdc
Collector Current I
C
100 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation
T
A
= 25°C
Derate above 25°C
P
D
246 (Note 1)
400 (Note 2)
2.0 (Note 1)
3.2 (Note 2)
mW
mW/°C
Thermal Resistance,
Junction-to-Ambient
R
q
JA
508 (Note 1)
311 (Note 2)
°C/W
Thermal Resistance,
Junction-to-Lead
R
q
JL
174 (Note 1)
208 (Note 2)
°C/W
Junction and Storage,
Temperature Range
T
J
, T
stg
−55 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−4 @ Minimum Pad
2. FR−4 @ 1.0 x 1.0 inch Pad
SOT−23
CASE 318
STYLE 6
MARKING
DIAGRAM
1
3
2
Preferred devices are recommended choices for future use
and best overall value.
PIN 3
COLLECTOR
(OUTPUT)
PIN 2
EMITTER
(GROUND)
PIN 1
BASE
(INPUT)
R1
R2
DEVICE MARKING INFORMATION
See specific marking information in the device marking table
on page 2 of this data sheet.
http://onsemi.com
1
A6x M G
G
A6x = Device Code
x = A − L (Refer to page 2)
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
Device Package Shipping
†
ORDERING INFORMATION
MMUN21xxLT1 SOT−23 3000/Tape & Reel
MMUN21xxLT3G SOT−23
(Pb−Free)
10000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
MMUN21xxLT1G SOT−23
(Pb−Free)
3000/Tape & Reel
MMUN21xxLT3 SOT−23 10000/Tape & Reel
