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AT45DB161-JC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AT45DB161
7
Note: 1. After power is applied and V
CC
is at the minimum specified datasheet value, the system should wait 20 ms before an opera-
tional mode is started.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
DC and AC Operating Range
AT45DB161
Operating Temperature
(Case)
Com. 0°C to 70°C
Ind. -40°C to 85°C
V
CC
Power Supply
(1)
2.7V to 3.6V
AT45DB161
8
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
SB
Standby Current CS, RESET, WP = V
IH
, all inputs at
CMOS levels
310µA
I
CC1
Active Current, Read Operation f = 13 MHz; I
OUT
= 0 mA; V
CC
= 3.6V 4 10 mA
I
CC2
Active Current, Program/Erase
Operation
V
CC
= 3.6V 15 35 mA
I
LI
Input Load Current V
IN
= CMOS levels 1 µA
I
LO
Output Leakage Current V
I/O
= CMOS levels 1 µA
V
IL
Input Low Voltage 0.6 V
V
IH
Input High Voltage 2.0 V
V
OL
Output Low Voltage I
OL
= 1.6 mA; V
CC
= 2.7V 0.4 V
V
OH
Output High Voltage I
OH
= -100 µA V
CC
- 0.2V V
AC Characteristics
Symbol Parameter Min Typ Max Units
f
SCK
SCK Frequency 13 MHz
t
WH
SCK High Time 35 ns
t
WL
SCK Low Time 35 ns
t
CS
Minimum CS High Time 250 ns
t
CSS
CS Setup Time 250 ns
t
CSH
CS Hold Time 250 ns
t
CSB
CS High to RDY/BUSY Low 200 ns
t
SU
Data In Setup Time 10 ns
t
H
Data In Hold Time 20 ns
t
HO
Output Hold Time 0 ns
t
DIS
Output Disable Time 25 ns
t
V
Output Valid 30 ns
t
XFR
Page to Buffer Transfer/Compare Time 250 350 µs
t
EP
Page Erase and Programming Time 10 20 ms
t
P
Page Programming Time 715ms
t
PE
Page Erase Time 610ms
t
BE
Block Erase Time 715ms
t
RST
RESET Pulse Width 10 µs
t
REC
RESET Recovery Time 1µs
Input Test Waveforms and Measurement Levels
t
R
, t
F
< 5 ns (10% to 90%)
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.45V
2.0
0.8
2.4V
Output Test Load
DEVICE
UNDER
TEST
30 pF
AT45DB161
9
AC Waveforms
Two different timing diagrams are shown below. Waveform
1 shows the SCK signal being low when CS
makes a high-
to-low transition, and Waveform 2 shows the SCK signal
being high when CS
makes a high-to-low transition. Both
waveforms show valid timing diagrams. The setup and hold
times for the SI signal are referenced to the low-to-high
transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI
Mode 0, and Waveform 2 shows timing that is compatible
with SPI Mode 3
Waveform 1 – Inactive Clock Polarity Low
Waveform 2 – Inactive Clock Polarity High
CS
SCK
SI
SO
tCSS
VALID IN
tHtSU
tWH tWL tCSH
tCS
tV
HIGH IMPEDANCE
VALID OUT
tHO tDIS
HIGH IMPEDANCE
CS
SCK
SI
SO
tCSS
VALID IN
tHtSU
tWL tWH tCSH
tCS
tV
HIGH Z
VALID OUT
tHO tDIS
HIGH IMPEDANCE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AT45DB161-JC

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Description:
IC FLASH 16M SPI 13MHZ 32PLCC
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