ZL30166GDG2

1
Microsemi Corporation
Copyright 2014, Microsemi Corporation. All Rights Reserved.
Features
Three programmable digital PLLs/Numerically
Controlled Oscillators (NCOs)
Synchronize to any clock rate from 1 KHz to
750 MHz
Four programmable synthesizers generate any
clock rate from 1 Hz to 750 MHz with low jitter for
10G PHYs
Flexible two-stage architecture translates between
arbitrary data rates, line coding rates and FEC
rates
Digital PLLs filter jitter from 5.2 Hz up to 1 kHz
Automatic hitless reference switching and digital
holdover on reference fail
Eight input references configurable as single ended
or differential
Any input reference can be fed with sync (frame
pulse) or clock
Programmable DPLLs can synchronize to sync
pulse and sync pulse/clock pair
Eight LVPECL outputs and eight LVCMOS outputs
Operates from a single crystal resonator or clock
oscillator
Field programmable via SPI/I
2
C interface
Applications
OTN muxponders and transponders
10 Gigabit line cards
Synchronous Ethernet, 10 GBASE-R and
10 GBASE-W
SONET/SDH, Fibre Channel, XAUI
October 2014
Reference Monitors
State Machine
Configuration
and Status
JTAG
Master Clock
ZL30166
Osci
Osco
Diff / Single Ended
Fr
0
= Br
0
*Kr
0
*Mr
0
/Nr
0
Ref0
JTAG
GPIO SPI / I
2
C
pwr_b
DPLL0/NCO0
Select Loop band.,
Phase slope limit
Ref7
Synthesizer 0
Fs= Bs
0
*Ks
0
*16*Ms
0
/Ns
0
LVPECL
LVCMOS
Div A
LVPECL
LVCMOS
Clock Generator 0
Div B
Div C
Div D
Synthesizer 1
Fs= Bs
1
*Ks
1
*16*Ms
1
/Ns
1
LVPECL
LVCMOS
Div A
LVPECL
LVCMOS
Clock Generator 1
Div B
Div C
Div D
Synthesizer 2
Fs= Bs
2
*Ks
2
*16*Ms
2
/Ns
2
LVPECL
LVCMOS
Div A
LVPECL
LVCMOS
Clock Generator 2
Div B
Div C
Div D
Synthesizer 3
Fs= Bs
3
*Ks
3
*16*Ms
3
/Ns
3
LVPECL
LVCMOS
Div A
LVPECL
LVCMOS
Clock Generator 3
Div B
Div C
Div D
Diff / Single Ended
Fr
7
= Br
7
*Kr
7
*Mr
7
/Nr
7
DPLL1/NCO1
Select Loop band.,
Phase slope limit
DPLL2/NCO2
Select Loop band.,
Phase slope limit
hpdiff1_p/n
hpoutclk0
hpdiff0_p/n
hpoutclk1
hpdiff3_p/n
hpoutclk2
hpdiff2_p/n
hpoutclk3
hpdiff5_p/n
hpoutclk4
hpdiff4_p/n
hpoutclk5
hpdiff7_p/n
hpoutclk6
hpdiff6_p/n
hpoutclk7
Ref5
Diff / Single Ended
Fr
5
= Br
5
*Kr
5
*Mr
5
/Nr
5
Ref4
Diff / Single Ended
Fr
4
= Br
4
*Kr
4
*Mr
4
/Nr
4
Ref3
Diff / Single Ended
Fr
3
= Br
3
*Kr
3
*Mr
3
/Nr
3
Ref2
Diff / Single Ended
Fr
2
= Br
2
*Kr
2
*Mr
2
/Nr
2
Ref1
Diff / Single Ended
Fr
1
= Br
1
*Kr
1
*Mr
1
/Nr
1
Ref6
Diff / Single Ended
Fr
6
= Br
6
*Kr
6
*Mr
6
/Nr
6
ZL30166
Triple Clock Translator
Product Brief
Ordering Information
ZL30166GDG2 144 Pin LBGA Trays
Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
Package Size: 13 x 13 mm
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ZL30166GDG2

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Triple Channel Clock Translator with Frame Sync Capability
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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