10
FN9231.2
March 28, 2008
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9001 provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 10µF output
capacitor that has a tolerance better than 20% and ESR less
than 200mΩ. The design is performance-optimized for a 1µF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not recommended as LDO
performance improvement is minimal.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge. The
ISL9001 provides short-circuit protection by limiting the
output current to about 425mA.
The LDO uses an independently trimmed 1V reference as its
input. An internal resistor divider drops the LDO output
voltage down to 1V. This is compared to the 1V reference for
regulation. The resistor division ratio is programmed in the
factory.
Power-On Reset Generation
The ISL9001 has a Power-on Reset signal generation
circuit, which indicates that output power is good. The POR
signal is generated as follows.
A POR comparator continuously monitors the output of the
LDO. The LDO enters a power-good state when the output
voltage is above 94% of the expected output voltage for a
period exceeding the LDO PGOOD entry delay time (see the
following). In the power-good state, the open-drain POR
output is in a high-impedance state. An internal 100k
Ω
pull-up resistor pulls the pin up to the LDO output voltage. An
external resistor can be added between the POR
output and
the LDO output for a faster rise time, however, the POR
output should not connect through an external resistor to a
supply greater than the LDO voltage.
The power-good state is exited when the LDO output falls
below 90% of the expected output voltage for a period longer
than the PGOOD exit delay time. While power-good is false,
the ISL9001 pulls the POR pin low.
The PGOOD entry and exit delays are determined by the
value of an external capacitor connected to the CPOR pin.
For a 0.01µF capacitor, the entry and exit delays are 200ms
and 25µs respectively. Larger or smaller capacitor values will
yield proportionately longer or shorter delay times. The POR
exit delay should never be allowed to be less than 10µs to
ensure sufficient immunity against transient induced false
POR triggering.
Overheat Detection
The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +140°C, if the LDO is
sourcing more than 50mA it shuts down until the die cools
sufficiently. Once the die temperature falls back below about
+110°C, the disabled LDO is re-enabled and soft-start
automatically takes place.
ISL9001
