LTC4245
20
4245fa
Power Bad Fault
A power bad condition exists when any supply output
drops below its power bad threshold for more than
15μs (17μs for V
EEOUT
). This sets bit A2 in the STATUS
register. The HEALTHY# output goes high impedance,
and LOCAL_PCI_RST# pin is pulled low. If the gate of
the supply’s MOSFET is enhanced, a power bad fault is
logged in bits F0 to F3 of the FAULT2 register. A circuit
will prevent power bad fault bits being set if the external
MOSFET gate-to-source voltage is low, eliminating false
power bad faults during power-up or power-down. If the
supply output subsequently rises back above the thresh-
old, bit A2 will be cleared, HEALTHY# will pull low and
LOCAL_PCI_RST# will follow PCI_RST#.
BD_SEL# Change of State
Whenever the BD_SEL# pin toggles, bit F6 is set to indi-
cate a change of state. When the BD_SEL# pin goes high,
indicating board removal, all switches turn off immediately.
Bit A6 reports the current state of this pin. If the BD_SEL#
pin is pulled low, indicating a board insertion, all fault bits
except F6 will be cleared. If the sequence bit C6 is set, then
On control bits D1 to D3 are also cleared. If the BD_SEL#
pin remains low for 100ms the state of the ON pin will
be captured in either D0 to D3 or only D0, depending on
sequence bit C6. This turns on the switches if ON pin is
tied high. There is an internal 10μA pull-up current source
on the BD_SEL# pin from INTV
CC
.
If the system shuts down due to a fault, it may be desirable
to restart the system simply by removing and reinserting
a load card. In cases where the LTC4245 and the switches
reside on a backplane or midplane (as in a PCI Express
application) and the load resides on a plug-in card, the
BD_SEL# pin can be used to detect when the plug-in card
is removed (see Figure 9). Once the plug-in card is rein-
serted the two fault registers are cleared (except for F6).
After 100ms the state of ON pin is latched into bits D0 to
D3. At this point the system will start up again.
If a connection sense on the plug-in card is driving the
BD_SEL# pin, the insertion or removal of the card may
cause the pin voltage to bounce. This will result in clear-
ing the fault register when the card is removed. The pin
can be debounced using a fi lter capacitor, C
BD_SEL#
, on
the BD_SEL# pin as shown in Figure 9. The fi lter time is
given by:
tC msµF
FILTER BD SEL
=
_#
•[/]123
(5)
FET Short Fault
A FET short fault will be reported if the data converter
measures a supply’s current sense voltage greater than 7
LSB while the supply’s pass transistor is turned off. This
condition sets the FET short present bit, A5, and the FET
short fault bit F5. Reading the On status bits (D4 to D7) and
the ADC current sense voltage data registers (J, M, P, S)
can help debug which supply’s MOSFET might be poten-
tially shorted. A false FET short fault might be reported if
an input supply power-up is delayed by more than 500ms
after INTV
CC
is up.
Fault Alerts
When any of the bits in fault registers E and F are set, an
optional bus alert can be generated by setting the appropri-
ate bit in the ALERT register B. This allows only selected
faults to generate alerts. At power-up the default state is not
to alert on faults. If an alert is enabled, the corresponding
fault will cause the ALERT# pin to pull low. See the Alert
Response Protocol section for more information.
APPLICATIO S I FOR ATIO
WUU
U
Figure 9. Plug-In Card Insertion/Removal
–
+
1.235V
GND
MOTHERBOARD
CONNECTOR PLUG-IN
CARD
LTC4245G*
*ADDITIONAL DETAILS OMITTED FOR CLARITY
10µA
9
BD_SEL# 10
C
BD_SEL#
4245 F09
