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L5970ADTR

P1-P3P4-P6P7-P9P10-P11
L5970AD
4/11
3 Functional Description
The main internal blocks are shown in Fig. 4, where is reported the device block diagram. They are:
● A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3V reference
voltage is externally available.
● A voltage monitor circuit that checks the input and internal voltages.
● A fully integrated sawtooth oscillator whose frequency is500KHz
● Two embedded current limitations circuitries which control the current that flows through the
power switch. The Pulse by Pulse Current Limit forces the power switch OFF cycle by cycle
if the current reaches an internal threshold, while the Frequency Shifter reduces the switch-
ing frequency in order to strongly reduce the duty cycle.
● A transconductance error amplifier.
● A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive
the internal power.
● An high side driver for the internal P-MOS switch.
● An inhibit block for stand-by operation.
● A circuit to realize the thermal protection function.
Figure 4. Block Diagram
3.1 POWER SUPPLY & VOLTAGE REFERENCE
The internal regulator circuit (shown in Figure 2) consists of a start-up circuit, an internal voltage Prereg-
ulator, the Bandgap voltage reference and the Bias block that provides current to all the blocks.
The Starter gives the start-up currents to the whole device when the input voltage goes high and the de-
vice is enabled (inhibit pin connected to ground).
The Preregulator block supplies the Bandgap cell with a preregulated voltage V
REG
that has a very low
supply voltage noise sensitivity.
3.2 VOLTAGES MONITOR
An internal block senses continuously the V
cc
, V
ref
and V
bg
. If the voltages go higher than their thresholds, the
regulator starts to work. There is also an hysteresis on the V
CC
(UVLO).
INHIBIT
VOLTAGES
MONITOR
PEAK TO PEAK
CURRENT LIMIT
THERMAL
SHUTDOWN
E/A
PWM
1.235V
+
-
-
+
OSCILLATOR
D
Ck
Q
FREQUENCY
SHIFTER
TRIMMING
SUPPLY
1.235V 3.5V
DRIVER
V
REF
BUFFER
LPDMOS
POWER
FB
SYNC
COMP
INH
V
REF
GND OUT
VCC
D00IN1125
5/11
L5970AD
Figure 5. Internal Regulator Circuit
3.3 OSCILLATOR & SYNCHRONIZATOR
Figure 6 shows the block diagram of the oscillator circuit.
The Clock Generator provides the switching frequency of the device that is internally fixed at 500KHz. The frequency
shifter block acts reducing the switching frequency in case of strong overcurrent or short circuit. The clock signal is
then used in the internal logic circuitry and is the input of the Ramp Generator and Synchronizator blocks.
The Ramp Generator circuit provides the sawtooth signal, used to realize the PWM control and the internal volt-
age feed forward, while the Synchronizator circuit generates the synchronization signal. Infact the device has a
synchronization pin that can works both as Master and Slave.
As Master to synchronize external devices to the internal switching frequency.
As Slave to synchronize itself by external signal.
In particular, connecting together two devices, the one with the lower switching frequency works as Slave and
the other one works as Master.
To synchronize the device, the SYNC pin has to pass from a low level to a level higher than the synchronization
threshold with a duty cycle that can vary approximately from 10% to 90%, depending also on the signal frequen-
cy and amplitude.
The frequency of the synchronization signal must be at least higher than the internal switching frequency of the
device (500KHz).
Figure 6. Oscillator Circuit
STARTER
IC BIAS
PREREGULATOR
BANDGAP
VREG
VREF
D00IN1126
V
CC
FREQUENCY
SHIFTER
CLOCK
GENERATOR
RAMP
GENERATOR
SYNCHRONIZATOR
CLOCK
RAMP
Ibias_osc
SYNC
t
D00IN1131
L5970AD
6/11
3.4 CURRENT PROTECTION
The L5970AD has two current limit protections, pulse by pulse and frequency fold back.
The schematic of the current limitation circuitry for the pulse by pulse protection is shown in figure 7.
The output power PDMOS transistor is split in two parallel PDMOS. The smallest one has a resistor in series,
R
SENSE
. The current is sensed through Rsense and if reaches the threshold, the mirror is unbalanced and the
PDMOS is switched off until the next falling edge of the internal clock pulse.
Due to this reduction of the ON time, the output voltage decreases.
Since the minimum switch ON time (necessary to avoid false overcurrent signal) is not enough to obtain a suf-
ficiently low duty cycle at 500KHz, the output current, in strong overcurrent or short circuit conditions, could in-
crease again. For this reason the switching frequency is also reduced, so keeping the inductor current under its
maximum threshold. The Frequency Shifter (see fig. 6) depends on the feedback voltage. As the feedback volt-
age decreases (due to the reduced duty cycle), the switching frequency decreases too.
Figure 7. Current Limitation Circuitry
3.5 ERROR AMPLIFIER
The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose
non inverting input is connected to the internal voltage reference (1.235V), while the inverting input (FB) is con-
nected to the external divider or directly to the output voltage. The output (COMP) is connected to the external
compensation network.
The uncompensated error amplifier has the following characteristics:
The error amplifier output is compared with the oscillator sawtooth to perform PWM control.
3.6 PWM COMPARATOR AND POWER STAGE
This block compares the oscillator sawtooth and the error amplifier output signals generating the PWM
signal for the driving stage.
The power stage is a very critical block cause it has to guarantee a correct turn on and turn off of the PD-
MOS.
Transconductance 2300µS
Low frequency gain 65dB
Minimum sink/source voltage 1500µA/300µA
Output voltage swing 0.4V/3.65V
Input bias current 2.5µA
DRIVER
NOT
A1
PWM
VCC
OUT
A1/A2=95
I
L
RSENSE
D00IN1134
I
OFF
II
RTH
A2
P1-P3P4-P6P7-P9P10-P11

L5970ADTR

Mfr. #:
Buy L5970ADTR
Manufacturer:
STMicroelectronics
Description:
Switching Voltage Regulators STEP DOWN MONOLITHIC SWITCH REG 1.5A
Lifecycle:
New from this manufacturer.
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