PROGRAMMABLE FANOUT BUFFER 4 REVISION D 07/13/15
5P1105 DATASHEET
Configuration and Input Descriptions
Table 2: Configuration Table
This table shows the SEL1, SEL0 settings to select the
configuration stored in OTP. Four configurations can be stored
in OTP. These can be factory programmed or user
programmed.
At power up time, the SEL0 and SEL1 pins must be tied to
either the VDDD/VDDA power supply so that they ramp with
that supply or are tied low (this is the same as floating the
pins). This will cause the register configuration to be loaded
that is selected according to Table 3 above. Providing that
OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after
the first 10mS of operation the levels of the SELx pins can be
changed, either to low or to the same level as VDDD/VDDA.
The SELx pins must be driven with a digital signal of < 300nS
Rise/Fall time and only a single pin can be changed at a time.
After a pin level change, the device must not be interrupted for
at least 1ms so that the new values have time to load and take
effect.
If OUT0_SEL_I2CB was 0 at POR, alternate configurations
can only be loaded via the I2C interface.
Table 3: Input Clock Select
Input clock select. Selects the active input reference source in
manual switchover mode.
0 = XIN/REF, XOUT (default)
1 = CLKIN, CLKINB
CLKSEL Polarity can be changed by I
2
C programming as
shown in Table 4.
PRIMSRC is bit 1 of Register 0x13.
21 V
DDO
1Power
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT1/OUT1B.
22 V
DDD
Power
Digital functions power supply pin. Connect to 1.8 to 3.3V. V
DDA
and V
DDD
should have the same voltage applied.
23 V
DDO
0Power
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT0.
24 OUT0_SEL_I2CB
Input/
Output
Internal
Pull-down
Latched input/LVCMOS Output. At power up, the voltage at the pin
OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8
and 9. If a weak pull up (10kohms) is placed on OUT0_SEL_I2CB, pins 8 and
9 will be configured as hardware select pins, SEL1 and SEL0. If a weak pull
down (10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and
9 will act as the SDA and SCL pins of an I
2
C interface. After power up, the pin
acts as a LVCMOS reference output.
ePAD GND GND Connect to ground pad.
Number Name Type Description
OUT0_SEL_I2CB
@ POR
SEL1 SEL0 I
2
C
Access
REG0:7 Config
100No00
101No01
110No02
111No03
0 X X Yes 1 I2C
defaults
0XXYes00
PRIMSRC CLKSEL Source
0 0 XIN/REF
0 1 CLKIN, CLKINB
1 0 CLKIN, CLKINB
1 1 XIN/REF
REVISION D 07/13/15 5 PROGRAMMABLE FANOUT BUFFER
5P1105 DATASHEET
Reference Clock Input Pins and
Selection
The 5P1105 supports up to two clock inputs. One input
supports a crystal between XIN and XOUT. XIN can also be
driven from a single ended reference clock. XIN can accept
small amplitude signals like from TCXO or one channel of a
differential clock.
The second clock input (CLKIN, CLKINB) is a fully differential
input that only accepts a reference clock. The differential input
accepts differential clocks from all the differential logic types
and can also be driven from a single ended clock on one of the
input pins.
The CLKSEL pin selects the input clock between either
XTAL/REF or (CLKIN, CLKINB).
Either clock input can be set as the primary clock. The primary
clock designation is to establish which is the main reference
clock. The non-primary clock is designated as the secondary
clock in case the primary clock goes absent and a backup is
needed. The PRIMSRC bit determines which clock input will
be selected as primary clock. When PRIMSRC bit is “0”,
XIN/REF is selected as the primary clock, and when “1”,
(CLKIN, CLKINB) as the primary clock.
The two external reference clocks can be manually selected
using the CLKSEL pin. The SM bits must be set to “0x” for
manual switchover which is detailed in Manual Switchover
Mode section.
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
A crystal manufacturer will calibrate its crystals to the nominal
frequency with a certain load capacitance value. When the
oscillator load capacitance matches the crystal load
capacitance, the oscillation frequency will be accurate. When
the oscillator load capacitance is lower than the crystal load
capacitance, the oscillation frequency will be higher than
nominal and vice versa so for an accurate oscillation
frequency you need to make sure to match the oscillator load
capacitance with the crystal load capacitance.
To set the oscillator load capacitance there are two tuning
capacitors in the IC, one at XIN and one at XOUT. They can
be adjusted independently but commonly the same value is
used for both capacitors. The value of each capacitor is
composed of a fixed capacitance amount plus a variable
capacitance amount set with the XTAL[5:0] register.
Adjustment of the crystal tuning capacitors allows for
maximum flexibility to accommodate crystals from various
manufacturers. The range of tuning capacitor values available
are in accordance with the following table.
XTAL[5:0] Tuning Capacitor Characteristics
The capacitance at each crystal pin inside the chip starts at
9pF with setting 000000b and can be increased up to 25pF
with setting 111111b. The step per bit is 0.5pF.
You can write the following equation for this capacitance:
Ci = 9pF + 0.5pF × XTAL[5:0]
The PCB where the IC and the crystal will be assembled adds
some stray capacitance to each crystal pin and more
capacitance can be added to each crystal pin with additional
external capacitors.
You can write the following equations for the total capacitance
at each crystal pin:
C
XIN
= Ci
1
+ Cs
1
+ Ce
1
C
XOUT
= Ci
2
+ Cs
2
+ Ce
2
Ci
1
and Ci
2
are the internal, tunable capacitors. Ci
1
and Cs
2
are stray capacitances at each crystal pin and typical values
are between 1pF and 3pF.
Ce
1
and Ce
2
are additional external capacitors that can be
added to increase the crystal load capacitance beyond the
tuning range of the internal capacitors. However, increasing
the load capacitance reduces the oscillator gain so please
consult the factory when adding Ce
1
and/or Ce
2
to avoid
crystal startup issues. Ce
1
and Ce
2
can also be used to adjust
for unpredictable stray capacitance in the PCB.
The final load capacitance of the crystal:
CL = C
XIN
× C
XOUT
/ (C
XIN
+ C
XOUT
)
For most cases it is recommended to set the value for
capacitors the same at each crystal pin:
C
XIN
= C
XOUT
= Cx CL = Cx / 2
The complete formula when the capacitance at both crystal
pins is the same:
CL = (9pF + 0.5pF × XTAL[5:0] + Cs + Ce) / 2
Parameter Bits Step (pF) Min (pF) Max (pF)
XTAL 6 0.5 9 25
PROGRAMMABLE FANOUT BUFFER 6 REVISION D 07/13/15
5P1105 DATASHEET
Example 1: The crystal load capacitance is specified as 8pF
and the stray capacitance at each crystal pin is Cs=1.5pF.
Assuming equal capacitance value at XIN and XOUT, the
equation is as follows:
8pF = (9pF + 0.5pF × XTAL[5:0] + 1.5pF) / 2
0.5pF × XTAL[5:0] = 5.5pF XTAL[5:0] = 11 (decimal)
Example 2
: The crystal load capacitance is specified as 12pF
and the stray capacitance Cs is unknown. Footprints for
external capacitors Ce are added and a worst case Cs of 5pF
is used. For now we use Cs + Ce = 5pF and the right value for
Ce can be determined later to make 5pF together with Cs.
12pF = (9pF + 0.5pF × XTAL[5:0] + 5pF) / 2
XTAL[5:0] = 20 (decimal)
Manual Switchover Mode
When SM[1:0] is “0x”, the redundant inputs are in manual
switchover mode. In this mode, CLKSEL pin is used to switch
between the primary and secondary clock sources. The
primary and secondary clock source setting is determined by
the PRIMSRC bit. During the switchover, no glitches will occur
at the output of the device, although there may be frequency
and phase drift, depending on the exact phase and frequency
relationship between the primary and secondary clocks.
OTP Interface
The 5P1105 can also store its configuration in an internal OTP.
The contents of the device's internal programming registers
can be saved to the OTP by setting burn_start (W114[3]) to
high and can be loaded back to the internal programming
registers by setting usr_rd_start(W114[0]) to high.
To initiate a save or restore using I
2
C, only two bytes are
transferred. The Device Address is issued with the read/write
bit set to “0”, followed by the appropriate command code. The
save or restore instruction executes after the STOP condition
is issued by the Master, during which time the 5P1105 will not
generate Acknowledge bits. The 5P1105 will acknowledge the
instructions after it has completed execution of them. During
that time, the I
2
C bus should be interpreted as busy by all
other users of the bus.
On power-up of the 5P1105, an automatic restore is
performed to load the OTP contents into the internal
programming registers. The 5P1105 will be ready to accept a
programming instruction once it acknowledges its 7-bit I
2
C
address.
Availability of Primary and Secondary I
2
C addresses to allow
programming for multiple devices in a system. The I
2
C slave
address can be changed from the default 0xD4 to 0xD0 by
programming the I2C_ADDR bit D0. VersaClock 5
Programming Guide provides detailed I
2
C programming
guidelines and register map.
SD/OE Pin Function
The polarity of the SD/OE signal pin can be programmed to be
either active HIGH or LOW with the SP bit (W16[1]). When SP
is “0” (default), the pin becomes active LOW and when SP is
“1”, the pin becomes active HIGH. The SD/OE pin can be
configured as either to shutdown the PLL or to enable/disable
the outputs. The SH bit controls the configuration of the
SD/OE pin The SH bit needs to be high for SD/OE pin to be
configured as SD
.
When configured as SD, device is shut down, differential
outputs are driven High/low, and the single-ended LVCMOS
outputs are driven low. When configured as OE, and outputs
are disabled, the outputs are driven high/low.
Table 4: SD/OE Pin Function Truth Table
SD/OE Input
SP
SH
OEn
OSn
Global Shutdown
OUTn
SH bit SP bit OSn bit OEn bit SD/OE OUTn
0 0 0 x x Tri-state
2
0 0 1 0 x Output active
0 0 1 1 0 Output active
0 0 1 1 1 Output driven High Low
0 1 0 x x Tri-state
2
0 1 1 0 x Output active
0 1 1 1 0 Output driven High Low
0 1 1 1 1 Output active
1 0 0 x 0 Tri-state
2
1 0 1 0 0 Output active
1 0 1 1 0 Output active
1 1 0 x 0 Tri-state
2
1 1 1 0 0 Output active
1 1 1 1 0 Output driven High Low
1x x x 1
Output driven High Low
1
Note 1 : Global Shutdown
Note 2 : Tri-state regardless of OEn bits

5P1105A000NLGI8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer Prog Clock Buffer V5 0.2ps 4 Out 4Banks
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