AD1974WBSTZ Datasheet AD1974WBSTZ, AD1974WBSTZ-RL, AD1974YSTZ-RL | P7-P9

AD1974 Data Sheet

Rev. D | Page 6 of 24

Parameter Condition Comments Min Max Unit

PLL

Lock Time MCLK and LRCLK input 10 ms

256 f

S

VCO Clock 40 60 %

Output Duty Cycle

MCLK_O Pin

SPI PORT See Figure 5

t

CCH

CCLK high 35 ns

t

CCL

CCLK low 35 ns

f

CCLK

CCLK frequency f

CCLK

= 1/t

CCP

; only t

CCP

shown in Figure 5

10 MHz

t

CDS

CDATA setup To CCLK rising 10 ns

t

CDH

CDATA hold From CCLK rising 10 ns

t

CLS

Setup To CCLK rising 10 ns

t

CLH

Hold From CCLK rising 10 ns

t

CLHIGH

High Not shown in Figure 5 10 ns

t

COE

COUT enable From CCLK falling 30 ns

t

COD

COUT delay From CCLK falling 30 ns

t

COH

COUT hold From CCLK falling, not shown in Figure 5 30 ns

t

COTS

COUT tristate From CCLK falling 30 ns

ADC SERIAL PORT See Figure 13

t

ABH

ABCLK high Slave mode 10 ns

t

ABL

ABCLK low Slave mode 10 ns

t

ALS

ALRCLK setup

To ABCLK rising, slave mode

10

ns

t

ALH

ALRCLK hold From ABCLK rising, slave mode 5 ns

t

ALS

ALRCLK skew From ABCLK falling, master mode −8 +8 ns

t

ABDD

ASDATA delay From ABCLK falling 18 ns

AUXILIARY INTERFACE See Figure 12

t

XDS

AAUXDATA setup To AUXBCLK rising 10 ns

t

XDH

AAUXDATA hold From AUXBCLK rising 5 ns

t

XBH

AUXBCLK high 10 ns

t

XBL

AUXBCLK low 10 ns

t

XLS

AUXLRCLK setup

To AUXBCLK rising

10

ns

t

XLH

AUXLRCLK hold From AUXBCLK rising 5 ns

Data Sheet AD1974

Rev. D | Page 7 of 24

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating

Analog (AVDD) −0.3 V to +3.6 V

Digital (DVDD) −0.3 V to +3.6 V

Input Current (Except Supply Pins) ±20 mA

Analog Input Voltage (Signal Pins) –0.3 V to AVDD + 0.3 V

Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V

Operating Temperature Range (Case) −40°C to +125°C

Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θ

JA

represents thermal resistance, junction-to-ambient; θ

JC

represents the thermal resistance, junction-to-case. All

characteristics are for a 4-layer board.

Table 9.

Package Type θ

JA

θ

JC

Unit

48-Lead LQFP 50.1 17 °C/W

ESD CAUTION

AD1974 Data Sheet

Rev. D | Page 8 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD

48

LF

47

ADC2RN

46

ADC2RP

45

ADC2LN

44

ADC2LP

43

ADC1RN

42

ADC1RP

41

ADC1LN

40

ADC1LP

39

CM

38

AVDD

37

DVDD

13

AUXDATA2

14

AUXDATA1

15

NC

16

AUXBCLK

17

AUXLRCLK

18

ASDATA2

19

ASDATA1

20

ABCLK

21

ALRCLK

22

CIN

23

COUT

24

AGND

1

MCLKI/XI

2

MCLKO/XO

3

AGND

4

AVDD

5

NC

6

NC

7

NC

NC = NO CONNECT

8

NC

9

PD/RST

10

NC

11

DGND

12

AGND

36

FILTR

35

AGND

34

AVDD

33

AGND

32

NC

31

NC

30

NC

29

NC

28

CLATCH

27

CCLK

26

DGND

25

AD1974

TOP VIEW

(Not to Scale)

SINGLE-ENDED

OUTPUT

06614-020

Figure 2. AD1974 Single-Ended Output, 48-Lead LQFP Pin Configuration

Table 10. Pin Function Description

Pin No.

Type

1

Mnemonic

Description

1, 4, 32, 34, 36 I AGND Analog Ground.

2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input.

3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output.

5, 33, 37, 48 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.

6 to 9, 11, 16, 28 to 31 NC No Connect.

10 I

PD

/

RST

Power-Down/Reset (Active Low).

12, 25

I

DGND

Digital Ground.

13

I

DVDD

Digital Power Supply. Connect to digital 3.3 V supply.

14 I/O AUXDATA2 Auxiliary Data Input 2 (From External ADC 2).

15 I/O AUXDATA1 Auxiliary Data Input 1 (From External ADC 1).

17 I/O AUXBCLK Auxiliary Bit Clock.

18 I/O AUXLRCLK Auxiliary Left-Right Framing Clock.

19 I/O ASDATA2 ADC Serial Data Output 2 (ADC 2 Left and ADC 2 Right)/ADC TDM Data Input.

20 O ASDATA1 ADC Serial Data Output 1 (ADC 1 Left and ADC 1 Right)/ADC TDM Data Output.

21 I/O ABCLK Serial Bit Clock for ADCs.

22 I/O ALRCLK Left-Right Framing Clock for ADCs.

23 I CIN Control Data Input (SPI).

24

I/O

COUT

Control Data Output (SPI).

26 I CCLK Control Clock Input (SPI).

27 I

CLATCH

Latch Input for Control Data (SPI).

35 O FILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND.

38 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with 47 µF||100 nF to AGND.

39 I ADC1LP ADC1 Left Positive Input.

40 I ADC1LN ADC1 Left Negative Input.

41 I ADC1RP ADC1 Right Positive Input.

42 I ADC1RN ADC1 Right Negative Input.

43 I ADC2LP ADC2 Left Positive Input.

AD1974WBSTZ

AD1974WBSTZ

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