DS80C310-QCG Datasheet DS80C310+FCG, DS80C310-QNG, DS80C310-MCG | P4-P6

DS80C310

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PDIP PLCC TQFP

NAME

FUNCTION

Port 3 (I/O). Port 3 functions as both an 8-bit bidirectional I/O port

and an alternate functional interface for external Interrupts, Serial

Port 0, Timer 0 and 1 Inputs, RD and WR strobes. The reset

condition of Port 3 is with all bits at logic 1. In this state, a weak

pullup holds the port high. This condition also serves as an input

mode, since any external circuit that writes to the port will overcome

the weak pullup. When software writes a 0 to any port pin, the

DS80C310 will activate a strong pulldown that remains on until

either a 1 is written or a reset occurs. Writing a 1 after the port has

been at 0 will cause a strong transition driver to turn on, followed by

a weaker sustaining pullup. Once the momentary strong driver turns

off, the port once again becomes both the output high and input

state. The alternate modes of Port 3 are as follows:

PDIP PLCC TQFP

PORT ALTERNATE FUNCTION

10 11 5 P3.0 RXD0

Serial Port 0

Input

11 13 7 P3.1 TXD0

Serial Port 0

Output

12 14 8 P3.2

INT0

External Interrupt

13 15 9 P3.3

INT1

External Interrupt

14 16 10 P3.4 T0

Timer 0 External

Input

15 17 11 P3.5 T1

Timer 1 External

Input

16 18 12 P3.6

External Data

Memory Write

Strobe

10–17

11,

13–19

5, 7–13 P3.0–P3.7

17 19 13 P3.7

External Data

Memory Read

Strobe

18, 19 20, 21 14, 15

XTAL2,

XTAL1

Crystal Oscillator Pins. XTAL1 and XTAL2 provide support for

parallel resonant, AT-cut crystals. XTAL1 also acts as an input in

the event that an external clock source is used in place of a crystal.

XTAL2 serves as the output of the crystal amplifier.

1, 22,

16, 17,

GND Digital Circuit Ground

21 24 18 A8 (P2.0)

22 25 19 A9 (P2.1)

23 26 20 A10 (P2.2)

24 27 21 A11 (P2.3)

25 28 22 A12 (P2.4)

26 29 23 A13 (P2.5)

27 30 24 A14 (P2.6)

28 31 25 A15 (P2.7)

Address Outputs (Port 2) (Output). Port 2 serves as the MSB for

external addressing. P2.7 is A15 and P2.0 is A8. The DS80C310

automatically places the MSB of an address on P2 for external ROM

and RAM access. Although Port 2 can be accessed like an ordinary

I/O port, the value stored on the Port 2 latch is never seen on the pins

(due to memory access). Therefore, writing to Port 2 in software is

only useful for the instructions MOVX A, @ Ri or MOVX @ Ri, A.

These instructions use the Port 2 internal latch to supply the external

address MSB; the Port 2 latch value is supplied as the address

information.

DS80C310

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PDIP PLCC TQFP

NAME

FUNCTION

29 32 26

PSEN

Active-Low Program Store Enable (Output). This signal is

commonly connected to external ROM memory as a chip enable.

PSEN is driven high when data memory (RAM) is being accessed

through the bus and during a reset condition.

30 33 27 ALE

Address Latch Enable (Output). The output functions as clock to

latch the external address LSB from the multiplexed address/data

bus on Port 0. This signal is commonly connected to the latch enable

of an external 373 family transparent latch. ALE is forced high when

the DS80C310 is in a reset condition.

31 35 29

Active-Low External Access (Input). This pin must be connected to

ground for proper operation.

32 36 30 AD7 (P0.7)

33 37 31 AD6 (P0.6)

34 38 32 AD5 (P0.5)

35 39 33 AD4 (P0.4)

36 40 34 AD3 (P0.3)

37 41 35 AD2 (P0.2)

38 42 36 AD1 (P0.1)

39 43 37 AD0 (P0.0)

Address/Data Bus 0–7 (Port 0) (I/O). Port 0 is the multiplexed

address/data bus. During the time when ALE is high, the LSB of a

memory address is presented. When ALE falls to logic 0, the port

transitions to a bidirectional data bus. This bus is used to read

external ROM and read/write external RAM memory or peripherals.

Port 0 has no true port latch and cannot be written directly by

software. The reset condition of Port 0 is high.

40 44 38 V

+5V Power Supply

– 12, 34 6, 28 N.C.

No Connection (Reserved). These pins should not be connected.

They are reserved for use with future devices in this family.

COMPATIBILITY

The DS80C310 is a fully static, CMOS, 8051-compatible microcontroller designed for high performance.

In most cases the DS80C310 can drop into an existing socket for the 80C31 or 80C32 to significantly

improve the operation. In general, software written for existing 8051-based systems works without

modification on the DS80C310. The exception is critical timing because the high-speed microcontroller

performs its instructions much faster than the original for any given crystal selection. The DS80C310 runs

the standard 8051 family instruction set and is pin compatible with DIP, PLCC, or TQFP packages. The

DS80C310 is a streamlined version of the DS80C320. It maintains upward compatibility but has fewer

peripherals.

The DS80C310 provides three 16-bit timer/counters, a full-duplex serial port, and 256 bytes of direct

RAM. I/O ports have the same operation as a standard 8051 product. Timers default to a 12 clock-per-

cycle operation to keep their timing compatible with original 8051 family systems. However, timers are

individually programmable to run at the new 4 clocks per cycle if desired.

The DS80C310 provides several new hardware functions that are controlled by Special Function

Registers (SFRs). Table 1 summarizes the SFRs.

PERFORMANCE OVERVIEW

The DS80C310 features a high-speed 8051-compatible core. Higher speed comes not just from increasing

the clock frequency but from a newer, more efficient design.

This updated core does not have the dummy memory cycles that exist in a standard 8051. A conventional

8051 generates machine cycles using the clock frequency divided by 12. In the DS80C310, the same

DS80C310

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machine cycle takes 4 clocks. Thus the fastest instruction, 1 machine cycle, executes three times faster for

the same crystal frequency. Note that these are identical instructions. The majority of instructions on the

DS80C310 will see the full 3-to-1 speed improvement. Some instructions will get between 1.5 and 2.4 to

1 improvement. All instructions are faster than the original 8051.

The numerical average of all op codes gives approximately a 2.5-to-1 speed improvement. Improvement

of individual programs depends on the actual instructions used. Speed-sensitive applications would make

the most use of instructions that are three times faster. However, the sheer number of 3-to-1 improved

op codes makes dramatic speed improvements likely for any code. These architecture improvements and

0.8m CMOS produce a peak instruction cycle in 160ns (6.25MIPS). The dual data pointer feature also

allows the user to eliminate wasted instructions when moving blocks of memory.

INSTRUCTION SET SUMMARY

All instructions in the DS80C310 perform the same functions as their 8051 counterparts. Their effect on

bits, flags, and other status functions is identical. However, the timing of each instruction is different.

This applies both in absolute and relative number of clocks.

For absolute timing of real-time events, the timing of software loops can be calculated using a table in the

High-Speed Microcontroller User’s Guide. However, counter/timers default to run at the older 12 clocks

per increment. In this way, timer-based events occur at the standard intervals with software executing at

higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor

operation.

The relative time of two instructions might be different in the new architecture than it was previously. For

example, in the original architecture the “MOVX A, @ DPTR” instruction and the “MOV direct, direct”

instruction used 2 machine cycles or 24 oscillator cycles. Therefore, they required the same amount of

time. In the DS80C310, the MOVX instruction takes as little as 2 machine cycles or 8 oscillator cycles

but the “MOV direct, direct” uses 3 machine cycles or 12 oscillator cycles. While both are faster than

their original counterparts, they now have different execution times. This is because the DS80C310

usually uses 1 instruction cycle for each instruction byte. The user concerned with precise program timing

should examine the timing of each instruction for familiarity with the changes. Note that a machine cycle

now requires just 4 clocks, and provides one ALE pulse per cycle. Many instructions require only 1 cycle,

but some require 5. In the original architecture, all were 1 or 2 cycles except for MUL and DIV. Refer to

the High-Speed Microcontroller User’s Guide for details and individual instruction timing.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

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