Data Sheet ADN4662
Rev. A | Page 3 of 12
SPECIFICATIONS
V
DD
= 3.0 V to 3.6 V; C
L
= 15 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
1
Symbol Min Typ
2
Max Unit Conditions/Comments
LVDS INPUT
High Threshold at R
IN+
, R
IN−
3
TH
+100
mV
V
CM
= 1.2 V, 0.05 V, 2.95 V
Low Threshold at R
IN+
, R
IN−
3
V
TL
−100 mV V
CM
= 1.2 V, 0.05 V, 2.95 V
Input Current at R
IN+
, R
IN−
I
IN
−10 ±1 +10 μA V
IN
= 2.8 V, V
CC
= 3.6 V or 0 V
−10 ±1 +10 μA V
IN
= 0 V, V
CC
= 3.6 V or 0 V
−20 ±1 +20 μA V
IN
= 3.6 V, V
CC
= 0 V
OUTPUT
Output High Voltage V
OH
2.7 3.1 V I
OH
= −0.4 mA, V
ID
= +200 mV
2.7 3.1 V I
OH
= −0.4 mA, input terminated
2.7
3.1
V
I
OH
= −0.4 mA, input shorted
Output Low Voltage V
OL
0.3 0.5 V I
OL
= 2 mA, V
ID
= −200 mV
Output Short-Circuit Current
4
I
OS
−15 −47 −100 mA Enabled, V
OUT
= 0 V
Input Clamp Voltage V
CL
−1.5 −0.8 V I
CL
= −18 mA
POWER SUPPLY
No Load Supply Current I
CC
5.4 9 mA Inputs open
ESD PROTECTION
R
IN+
, R
IN−
Pins ±15 kV Human body model
All Pins Except R
IN+
, R
IN−
±4 kV Human body model
1
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground, unless otherwise specified.
2
All typicals are given for: V
CC
= +3.3 V, T
A
= 25°C.
3
V
CC
is always higher than R
IN+
and R
IN
voltage. R
IN
and R
IN+
are allowed to have a voltage range of −0.2 V to V
CC
− V
ID
/2. However, to be compliant with ac specifications,
the common voltage range is 0.1 V to 2.3 V.
4
Output short-circuit current (I
OS
) is specified as magnitude only; the minus sign indicates direction only. Only one output should be shorted at a time. Do not exceed
maximum junction temperature specification.
ADN4662 Data Sheet
Rev. A | Page 4 of 12
AC CHARACTERISTICS
V
DD
= 3.0 V to 3.6 V; C
L
1
= 15 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ
2
Max Unit Conditions/Comments
3
Differential Propagation Delay High to Low t
PHLD
1.0 2.15 2.5 ns C
L
= 15 pF, V
ID
= 200 mV (see Figure 2 and Figure 3)
Differential Propagation Delay Low to High t
PLHD
1.0 2.03 2.5 ns C
L
= 15 pF, V
ID
= 200 mV (see Figure 2 and Figure 3)
Differential Pulse Skew |t
PHLD
− t
PLHD
|
4
t
SKD1
0 80 400 ps C
L
= 15 pF, V
ID
= 200 mV (see Figure 2 and Figure 3)
Differential Part-to-Part Skew
5
t
SKD3
1.0 ns C
L
= 15 pF, V
ID
= 200 mV (see Figure 2 and Figure 3)
Differential Part-to-Part Skew
6
t
SKD4
1.5 ns C
L
= 15 pF, V
ID
= 200 mV (see Figure 2 and Figure 3)
Rise Time
t
TLH
510
800
ps
C
L
= 15 pF, V
ID
= 200 mV (see Figure 2 and Figure 3)
Fall Time t
THL
445 800 ps C
L
= 15 pF, V
ID
= 200 mV (see Figure 2 and Figure 3)
Maximum Operating Frequency
7
f
MAX
200 250 MHz All channels switching
1
C
L
includes probe and jig capacitance.
2
All typicals are given for V
CC
= 3.3 V, T
A
= 25°C.
3
Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50, t
TLH
and t
THL
(0% to 100%) ≤ 3 ns for R
IN+
/R
IN−
.
4
t
SKD1
is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel.
5
t
SKD3
, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V
CC
and within 5°C
of each other within the operating temperature range.
6
t
SKD4
, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating
temperature and voltage ranges, and across process distribution. t
SKD4
is defined as |maximum minimum| differential propagation delay.
7
f
MAX
generator input conditions: f = 200 MHz, t
TLH
= t
THL
< 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V to 1.35 V peak-to-peak). Output criteria: 60%/40% duty
cycle, V
OL
(maximum 0.4 V), V
OH
(minimum 2.7 V), load = 15 pF (stray plus probes).
Data Sheet ADN4662
Rev. A | Page 5 of 12
Test Circuits and Timing Diagrams
V
CC
R
OUT
R
IN+
C
L
SIGNAL
GENERATOR
50Ω 50Ω
R
IN–
C
L
= LOAD AND TEST JIG CAPACITANCE
07960-002
Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time
20%
80%
80%
20%
1.5V
1.5V
t
PLHD
t
PHLD
R
IN–
R
IN+
0V (DIFFERENTIAL)
t
TLH
t
THL
V
OH
V
OL
1.2V
1.3V
1.1V
R
OUT
V
ID
= 200mV
07960-003
Figure 3. Receiver Propagation Delay and Transition Time Waveforms

ADN4662BRZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
LVDS Interface IC SGL 3V CMOS Diff Line Receiver
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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