AS3PGHM3/86A Datasheet AD7780BRUZ, AD7780BRZ, AD7780BRUZ-REEL | P13-P15

AD7780

Rev. A | Page 12 of 16

GAIN

The AD7780 has two gain options: gain = 1 and gain = 128.

When the GAIN pin is low, the gain is set to 128; when the

GAIN pin is high, the gain is set to 1. The acceptable analog

input range is ±V

REF

/gain. Thus, with V

REF

= 5 V, the input range

is ±5 V when the GAIN pin is high and ±39 mV when the GAIN

pin is low.

When the polarity of the GAIN pin is changed, the AD7780 modu-

lator and filter are reset immediately. DOUT/

RDY

is set high, and

the ADC then begins conversions. DOUT/

RDY

remains high until

the appropriate settling time for the filter elapses (see ).

Therefore, the user should complete any read operations before

changing the gain. Otherwise, 1s are read back from the AD7780

because the DOUT/

Figure 5

RDY

pin is set high following the gain change.

The total settling time of the selected filter is required to generate

the first conversion after the gain change; subsequent conversions

occur at the selected update rate.

POWER-DOWN/RESET (PDRST)

The

PDRST

pin functions as a power-down pin and a reset pin.

When

PDRST

is taken low, the AD7780 is powered down. The

entire ADC is powered down (including the on-chip clock), the

low-side power switch is opened, and the DOUT/

RDY

pin is

tristated. The circuitry and serial interface are also reset, which

resets the logic, the digital filter, and the analog modulator.

PDRST

must be held low for 100 ns minimum to initiate the

reset function (see ) . Figure 4

When

PDRST

is taken high, the AD7780 is taken out of power-

down mode. When the on-chip clock has powered up (1 ms,

typically), the modulator begins sampling the analog input. The

low-side power switch is closed, and the DOUT/

RDY

becomes active.

A reset is automatically performed on power-up.

ANALOG INPUT CHANNEL

The AD7780 has one differential analog input channel. The

input channel feeds into a high impedance input stage of the

amplifier. Therefore, the input can tolerate significant source

impedances and is tailored for direct connection to external

resistive-type sensors such as strain gages.

The absolute input voltage range is restricted to a range between

GND + 300 mV and AV

− 1.1 V. Care must be taken in setting

up the common-mode voltage to avoid exceeding these limits.

Otherwise, there is degradation in linearity and noise performance.

The low noise in-amp means that signals of small amplitude can

be amplified within the AD7780, while maintaining excellent noise

performance. The amplifier can be configured to have a gain of 128

or 1, using the GAIN pin. The analog input range is equal to

±V

REF

/gain. The common-mode voltage (AIN(+) + AIN(−))/2

must be ≥0.5 V.

BIPOLAR CONFIGURATION

The AD7780 accepts a bipolar input range. A bipolar input range

does not imply that the part can tolerate negative voltages with

respect to system GND. Signals on the AIN(+) input are refer-

enced to the voltage on the AIN(−) input. For example, if AIN(−)

is 2.5 V, the analog input range on the AIN(+) input is 2.46 V to

2.54 V for a gain of 128.

DATA OUTPUT CODING

The AD7780 uses offset binary coding. Thus, a negative full-

scale voltage results in a code of 000...000, a zero differential

input voltage results in a code of 100...000, and a positive full-

scale input voltage results in a code of 111...111.

The output code for any analog input voltage can be represented as

Code = 2

N − 1

× [(AIN × Gain /V

REF

) + 1]

where:

AIN is the analog input voltage.

Gain is 1 or 128.

N = 24.

REFERENCE

The AD7780 has a fully differential input capability for the channel.

The common-mode range for these differential inputs is GND to

. The reference input is unbuffered; therefore, excessive R-C

source impedances introduce gain errors. The reference voltage of

REFIN (REFIN(+) − REFIN(−)) is AV

nominal, but the AD7780

is functional with reference voltages of 0.5 V to AV

. In applica-

tions where the excitation (voltage or current) for the transducer

on the analog input also drives the reference voltage for the part,

the effect of the low frequency noise in the excitation source is

removed because the application is ratiometric. If the AD7780

is used in a nonratiometric application, a low noise reference

should be used.

Recommended 2.5 V reference voltage sources for the AD7780

include the ADR381 and ADR391, which are low noise, low

power references. These references have low output impedances

and are, therefore, tolerant to decoupling capacitors on REFIN(+)

without introducing gain errors in the system. Deriving the

reference input voltage across an external resistor means that

the reference input sees a significant external source impedance.

External decoupling on the REFIN pins is not recommended in

this type of circuit configuration.

AD7780

Rev. A | Page 13 of 16

DOUT/

RDY

is reset high when the conversion has been read.

If the conversion is not read, DOUT/

RDY

goes high prior to the

data register update to indicate when not to read from the device.

This ensures that a read operation is not attempted while the reg-

ister is being updated. Each conversion can be read only once. The

data register is updated for every conversion. When a conversion

is complete, the serial interface is reset, and the new conversion is

placed in the data register. Therefore, the user must ensure that

the complete word is read before the next conversion is complete.

BRIDGE POWER-DOWN SWITCH

The bridge power-down switch (BPDSW) is useful in battery-

powered applications where the optimization of system power

consumption is essential. A 350  load cell typically consumes

15 mA when excited with a 5 V power supply. To minimize the

current consumption, the load cell is disconnected when it is

not being used. The bridge power-down switch can be included

in series with the load cell. When

PDRST

is high, the bridge power-

down switch is closed, and the load cell measures the strain. When

PDRST

is low, the bridge power-down switch is opened so no

current flows through the load cell. Therefore, the current

consumption of the system is minimized. The bridge power-

down switch has an on resistance of 9  maximum. The switch

is capable of withstanding 30 mA of continuous current.

When

PDRST

is low, the DOUT/

RDY

pin is tristated. When

PDRST

is taken high, the internal clock requires approximately

1 ms to power up. Following power-up, the ADC continuously

converts. The first conversion requires the total settling time (see

). DOUT/Figure 4

RDY

goes high when

PDRST

is taken high and

returns low only when a conversion is available. The ADC then

converts continuously, and subsequent conversions are avail-able

at the selected update rate. shows the timing for a read

operation from the AD7780.

Figure 3

DIGITAL INTERFACE

The serial interface of the AD7780 consists of two signals: SCLK

and DOUT/

RDY

. SCLK is the serial clock input for the device,

and data transfers occur with respect to the SCLK signal. The

DOUT/

RDY

pin is dual purpose: it functions as a data ready pin

and as a data output pin. DOUT/

RDY

goes low when a new

data-word is available in the output register. A 32-bit word is

placed on the DOUT/

RDY

pin when sufficient SCLK pulses are

applied. This word consists of a 24-bit conversion result and eight

status bits. shows the status bits, and describes

the status bits and their functions.

Figure 22 Table 9

When the filter response is changed (using FILTER) or the gain

is changed (using GAIN), the modulator and filter are reset

immediately (see Figure 5). DOUT/

RDY

is set high. The ADC

then begins conversions using the selected filter response/gain

setting. DOUT/

RDY

remains high until the appropriate settling

time for that filter has elapsed. Therefore, the user should complete

any read operations before changing the gain or update rate.

Otherwise, 1s are read back from the AD7780 because the

DOUT/

RDY

pin is set high following the gain/filter change.

07945-121

FILTER ERRRDY ID1 ID0 GAIN PAT1 PAT0

Figure 22. Status Bits

Table 9. Status Bit Functions

Bit Name Description

RDY

Ready bit.

0: a conversion is available.

FILTER Filter bit.

1: 10 Hz filter is selected

0: 16.7 Hz filter is selected.

ERR Error bit.

1: an error occurred during conversion. (An error occurs when the analog input is outside the range.)

ID1, ID0 ID bits.

ID1 ID0 Function

0 1 Indicates the ID number for the AD7780

GAIN Gain bit.

1: gain = 1.

0: gain = 128.

PAT1, PAT0 Status pattern bits. When the user reads data from the AD7780, a pattern check can be performed.

PAT1 PAT0 Function

0 1 Indicates that the serial transfer from the ADC was performed correctly (default).

0 0 Indicates that the serial transfer from the ADC was not performed correctly.

1 0 Indicates that the serial transfer from the ADC was not performed correctly.

1 1 Indicates that the serial transfer from the ADC was not performed correctly.

AD7780

Rev. A | Page 14 of 16

APPLICATIONS INFORMATION

The AD7780 provides a low cost, high resolution analog-to-digital

function. Because the analog-to-digital function is provided by a

Σ- architecture, the parts are more immune to noisy environ-

ments, making them ideal for use in sensor measurement and

industrial and process control applications.

WEIGH SCALES

Figure 23 shows the AD7780 being used in a weigh scale

application. The load cell is arranged in a bridge network and

gives a differential output voltage between its OUT+ and OUT−

terminals. Assuming a 5 V excitation voltage, the full-scale

output range from the transducer is 10 mV when the sensitivity

is 2 mV/V. The excitation voltage for the bridge can be used to

directly provide the reference for the ADC because the refer-

ence input range includes the supply voltage.

A second advantage of using the AD7780 in transducer-based

applications is that the bridge power-down switch (BPDSW)

can be fully utilized in low power applications. The bridge power-

down switch is connected in series with the low side of the bridge.

In normal operation, the switch is closed and measurements

can be taken. In applications where power is of concern, the

AD7780 can be placed in power-down mode, significantly

reducing the power consumed in the application. In addition,

the bridge power-down switch is opened while in power-down

mode, thus avoiding unnecessary power consumption by the

front-end transducer. When the part is taken out of power-down

mode and the bridge power-down switch is closed, the user should

ensure that the front-end circuitry is fully settled before attempting

a read from the AD7780.

The load cell has an offset or tare associated with it. This tare is

the main component of the system offset (load cell + ADC) and is

similar in magnitude to the full-scale signal from the load cell.

For this reason, calibrating the offset and gain of the AD7780 alone

is not sufficient for optimum accuracy; a system calibration that

calibrates the offset and gain of the ADC, plus the load cell, is

required. A microprocessor can be used to perform the calibra-

tions. The offset (the conversion result from the AD7780 when

no load is applied to the load cell) and the full-scale error (the

conversion result from the ADC when the maximum load is

applied to the load cell) must be determined. Subsequent conver-

sions from the AD7780 are then corrected, using the offset and

gain coefficients that were calculated from these calibrations.

PERFORMANCE IN A WEIGH SCALE SYSTEM

If the load cell has a sensitivity of 2 mV/V and a 5 V excitation

voltage is used, the full-scale signal from the load cell is 10 mV.

When the AD7780 operates with a 10 Hz output data rate and

the gain is set to 128, the device has a p-p resolution of 18.2 bits

when the reference is equal to 5 V. Postprocessing the data from

the AD7780 using a microprocessor increases the p-p resolution.

For example, an average by 4 in the microprocessor increases

the accuracy by 2 bits. The noise-free counts is equal to the

following:

Noise-Free Counts = (2

Effective Bits

)(FS

/FS

ADC

)

where:

Effective Bits = 18.2 bits + 2 bits (due to post-processing in the

microprocessor).

is the full-scale signal from the load cell (10 mV).

ADC

is the full-scale input range when gain = 128 and V

REF

= 5 V

(78 mV).

The noise-free counts are equal to the following:

18.2 + 2

)(10 mV/78 mV) = 154,422

This example shows that with a 5 V supply, 154,422 noise-free

counts can be achieved with the AD7780.

EMI RECOMMENDATIONS

For simplicity, the EMI filters are not included in Figure 23.

However, an R-C antialiasing filter should be included on each

analog input. This filter is needed because the on-chip digital

filter does not provide any rejection around the master clock or

multiples of the master clock. Suitable values are a 1 kΩ resistor

in series with each analog input, a 0.1 F capacitor from AIN(+)

to AIN(−), and 0.01 F capacitors from AIN(+)/AIN(−) to GND.

G = 1

OR 128

24-BIT Σ-Δ

ADC

DOUT/RDY

GND AV

AIN(+)

REFIN(+)

AIN(–)

SCLK

FILTER

GAIN

INTERNAL

CLOCK

AD7780

PDRST

BPDSW

REFIN(–)

OUT–

IN+

IN–

OUT+

7945-022

Figure 23. Weigh Scales Using the AD7780

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

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