IDT 89HPES32NT24AG2 Datasheet
15 of 38 December 17, 2013
Reference Clocks GCLKN[1:0] I HCSL Diff. Clock
Input
Refer to Table 11
Note: Unused port
clock pins should be
connected to Vss on
the board.
GCLKP[1:0] I
P00CLKN I
P00CLKP I
P02CLKN I
P02CLKP I
P04CLKN I
P04CLKP I
P06CLKN I
P06CLKP I
P08CLKN I
P08CLKP I
P12CLKN I
P12CLKP I
P16CLKN I
P16CLKP I
P20CLKN I
P20CLKP I
SMBus MSMBCLK I/O LVTTL STI
3
Note: When unused, these signals
must be pulled up on the board using
an external resistor or current source in
accordance with the SMBus specifica-
tion.
MSMBDAT I/O STI
SSMBADDR[2,1] I pull-up
SSMBCLK I/O STI Note: When unused, these signals
must be pulled up on the board using
an external resistor or current source in
accordance with the SMBus specifica-
tion.
SSMBDAT I/O STI
General Purpose I/O GPIO[8:0] I/O LVTTL STI, High
Drive
pull-up Unused pins can be
left floating.
Stack Configuration STK0CFG[1:0] I LVTTL Input pull-down Unused pins can be
left floating.
STK1CFG[1:0] I pull-down
STK2CFG[4:0] I pull-down
STK3CFG[4:0] I pull-down
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
1
Notes
Table 10 Pin Characteristics (Part 4 of 5)
