NCP133
www.onsemi.com
7
APPLICATIONS INFORMATION
IN
EN FB
LX
GND
Processor
I/O
BIAS
IN
OUT
GND
NCP133
LOAD
VBAT
1.5 V
1.0 V
To other circuits
I/O
EN
Figure 12. Typical Application: Low−Voltage DC/DC Post−Regulator with ON/OFF Functionality
Switch−mode DC/DC
V
OUT
= 1.5 V
The NCP133 dual−rail very low dropout voltage regulator
is using NMOS pass transistor for output voltage regulation
from V
IN
voltage. All the low current internal control
circuitry is powered from the V
BIAS
voltage.
The use of an NMOS pass transistor offers several
advantages in applications. Unlike PMOS topology devices,
the output capacitor has reduced impact on loop stability.
Vin to Vout operating voltage difference can be very low
compared with standard PMOS regulators in very low Vin
applications.
The NCP133 offers smooth monotonic start-up. The
controlled voltage rising limits the inrush current.
The Enable (EN) input is equipped with internal
hysteresis. NCP133 Voltage linear regulator Fixed and
Adjustable version is available.
Output Voltage Adjust
The required output voltage of Adjustable devices can be
adjusted from 0.8 V to 3.6 V using two external resistors.
Typical application schematics is shown in Figure 13.
BIAS
IN
OUT
GND
C
BIAS
2.2
μF
C
IN
NCP133 ADJ
V
BIAS
V
IN
EN
V
EN
V
OUT
ADJ
R1
R2
Figure 13. Typical Application Schematics
V
OUT
+ 0.8
ǒ
1 ) R1ńR2
Ǔ
It is recommended to keep the total serial resistance of
resistors (R1 + R2) no greater than 100 kW.
Recommended resistor values for programming the
frequently used voltages can be found in the Table 1.
Dropout Voltage
Because of two power supply inputs V
IN
and V
BIAS
and
one V
OUT
regulator output, there are two Dropout voltages
specified.
The first, the V
IN
Dropout voltage is the voltage
difference (V
IN
– V
OUT
) when V
OUT
starts to decrease by
percent specified in the Electrical Characteristics table.
V
BIAS
is high enough; specific value is published in the
Electrical Characteristics table.
The second, V
BIAS
dropout voltage is the voltage
difference (V
BIAS
– V
OUT
) when V
IN
and V
BIAS
pins are
joined together and V
OUT
starts to decrease.
Input and Output Capacitors
The device is designed to be stable for ceramic output
capacitors with Effective capacitance in the range from
2.2 mF to 10 mF. The device is also stable with multiple
capacitors in parallel, having the total effective capacitance
in the specified range.
In applications where no low input supplies impedance
available (PCB inductance in V
IN
and/or V
BIAS
inputs as
example), the recommended C
IN
= 1 mF and C
BIAS
= 0.1 mF
or greater. Ceramic capacitors are recommended. For the
best performance all the capacitors should be connected to
the NCP133 respective pins directly in the device PCB
copper layer, not through vias having not negligible
impedance.
When using small ceramic capacitor, their capacitance is
not constant but varies with applied DC biasing voltage,
temperature and tolerance. The effective capacitance can be
much lower than their nominal capacitance value, most
importantly in negative temperatures and higher LDO
output voltages. That is why the recommended Output
capacitor capacitance value is specified as Effective value in
the specific application conditions.
