Copyright © 2013 Microsemi
Rev. 1.7, 17-July-2013 Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
16
1 Port PSE PoE PD69101 Controller
L
L
X
X
1
1
9
9
7
7
6
6
WWW.Microsemi .COM
PD69101
4 P A I R T Y P I C A L T I M I N G D I A G R A M
t
slave
t
456 msec detection cycle
Class
detection
master
Class
SYNC
Signal
startup
ongoing
detection
slave waits for 16
consecutive clks of
sync high
(~2usec)
Figure 5: 4 Pair Timing Diagram
Serial Communication - Monitoring Mode
When Mode0 and Mode1 Input pins are configured to Serial Monitoring Mode (“01”), the PD69101 transmits out
(continuously and repeatedly) the content of 9 internal registers:
Data Out Stream is transmitted through LED1 (pin 14)
Clock Out Stream is transmitted through LED0 (pin 13)
Data stream is shifted out with a 1 MHz clock (1 µsec).
Total transaction packet length is 116 µsec.
The transmission is repeated every 1 msec.
Between transactions the clock is held low, while data stream out is stable high/low.
Note: To exploit LED1 and LED0 to communicate and monitor transmissions, use a 1 K pull-up resistor to the DVDD.
Copyright © 2013 Microsemi
Rev. 1.7, 17-July-2013 Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
17
1 Port PSE PoE PD69101 Controller
L
L
X
X
1
1
9
9
7
7
6
6
WWW.Microsemi .COM
PD69101
Table 5: Stream Out Data Transmits 116 bits Starting from MSB to LSB
M S B Y TE
L S B Y TE
I N T E R N AL
0
I N T E R N AL
1
I N T E R N AL
2
I N T E R N AL
3
I N T E R N AL
4
V P O R T
V M AI N
I P O R T
P O R T
S T AT U S
1 3 B I T S
1 0 B I T S
2 3 B I T S
1 6 B I T S
1 6 B I T S
1 0 B I T S
1 0 B I T S
1 3 B I T S
5 B I TS
78 internal signals used for internal tests
Port voltage
measurement
LSB = 58 mV
V = Decimal x
58 mV
Vmain
voltage
measurement
LSB = 58 mV
V = Decimal
x 58 mV
Port current
measurement
LSB =
238 uA
I = Decimal x
238 uA
Real time
port status
indication
See
coding
table
below
Table 6: Port Status Coding
B I N A R Y M S B T O L S B
D E C I M A L V A L U E
D E S C R I P T I O N
00000
00001
00010
0
1
2
POE idle state
00011
3
Searching phase
00100
4
Res detection phase
00101
00110
5
6
Back off phase
00111
01000
7
8
Class phase
01001
01010
01100
9
10
12
Wait for start up
01011
11
Cap detection
01101
01110
13
14
Start up
01111
10000
15
16
On going
10001
17
UDL
10010
18
Overload or short circuit
10011
10100
19
20
Vmain out of range
9
8
1 0
Vport MeasureInternal BITS
78 x
MSB LSB
116 x clk cycles
9
8 1 0
MSB LSB
4
3
2 1
MSB
LSB
0
Port Status
Clock Out
(Pin 13)
Data Out
(Pin 14)
Figure 6: Data Stream Out
Copyright © 2013 Microsemi
Rev. 1.7, 17-July-2013 Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
18
1 Port PSE PoE PD69101 Controller
L
L
X
X
1
1
9
9
7
7
6
6
WWW.Microsemi .COM
PD69101
Data Packet
116uS
Idle Data Packet
116uS
1mS
Clock Out
(Pin 13)
Figure 7: Multi Packet Idle Time (Between Packets)
500nS500nS
Typ Typ
Clock Out
(Pin 13)
Data Out
(Pin 14)
Figure 8: Data / Clock Typical Timing

PD69101ILQ-13155TR

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Power Switch ICs - POE / LAN PoE PSE Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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