LPC2114_2124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 10 June 2011 4 of 42
NXP Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
4. Block diagram
(1) Shared with GPIO.
(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(3) SSP interface and high-speed GPIO are available on LPC2114/01 and LPC2124/01 only.
Fig 1. Block diagram
SCL
(1)
P0[30:27],
P0[25:0]
TRST
(2)
TMS
(2)
TCK
(2)
TDI
(2)
TDO
(2)
XTAL2
XTAL1
EINT[3:0]
(1)
AIN[3:0]
(1)
PWM[6:1]
(1)
AHB BRIDGE
PLL
PWM0
ARM7TDMI-S
LPC2114
LPC2124
P0[30:27],
P0[25:0]
RESET
P1[31:16]
4 × CAP0
(1)
4 × CAP1
(1)
4 × MAT0
(1)
4 × MAT1
(1)
P1[31:16]
SDA
(1)
DSR1
(1)
, CTS1
(1)
,
RTS1
(1)
, DTR1
(1)
,
DCD1
(1)
, RI1
(1)
RTCK
(2)
HIGH-SPEED
GPIO
(3)
46 PINS TOTAL
ARM7 LOCAL BUS
INTERNAL
SRAM
CONTROLLER
MEMORY
ACCELERATOR
16 kB
SRAM
128/256 kB
FLASH
EXTERNAL
INTERRUPTS
CAPTURE/
COMPARE
TIMER 0/TIMER 1
A/D CONVERTER
GENERAL
PURPOSE I/O
REAL-TIME CLOCK
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
AMBA Advanced High-performance
Bus (AHB)
system
clock
SYSTEM
FUNCTIONS
VECTORED
INTERRUPT
CONTROLLER
AHB
DECODER
I
2
C-BUS SERIAL
INTERFACE
AHB TO APB
BRIDGE
APB
DIVIDER
SPI0
SERIAL INTERFACE
UART0/UART1
WATCHDOG
TIMER
SYSTEM
CONTROL
002aad175
SCK0
(1)
MOSI0
(1)
MISO0
(1)
SSEL0
(1)
SPI1/SSP
(3)
SERIAL INTERFACE
SCK1
(1)
MOSI1
(1)
MISO1
(1)
SSEL1
(1)
RXD[1:0]
(1)
TXD[1:0]
(1)
LPC2114_2124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 10 June 2011 5 of 42
NXP Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
5. Pinning information
5.1 Pinning
(1) Pin configuration is identical for devices with and without the /00 and /01 suffixes.
Fig 2. Pin configuration
LPC2114
LPC2124
(1)
P0[21]/PWM5/CAP1[3] P1[20]/TRACESYNC
P0[22]/CAP0[0]/MAT0[0] P0[17]/CAP1[2]/SCK1/MAT1[2]
P0[23] P0[16]/EINT0/MAT0[2]/CAP0[2]
P1[19]/TRACEPKT3 P0[15]/RI1/EINT2
P0[24] P1[21]/PIPESTAT0
V
SS
V
DD(3V3)
V
DDA(3V3)
V
SS
P1[18]/TRACEPKT2 P0[14]/DCD1/EINT1
P0[25] P1[22]/PIPESTAT1
n.c. P0[13]/DTR1/MAT1[1]
P0[27]/AIN0/CAP0[1]/MAT0[1] P0[12]/DSR1/MAT1[0]
P1[17]/TRACEPKT1 P0[11]/CTS1/CAP1[1]
P0[28]/AIN1/CAP0[2]/MAT0[2] P1[23]/PIPESTAT2
P0[29]/AIN2/CAP0[3]/MAT0[3] P0[10]/RTS1/CAP1[0]
P0[30]/AIN3/EINT3/CAP0[0] P0[9]/RXD1/PWM6/EINT3
P1[16]/TRACEPKT0 P0[8]/TXD1/PWM4
V
DD(1V8)
P1[27]/TDO
V
SS
V
DDA(1V8)
P0[0]/TXD0/PWM1 XTAL1
P1[31]/TRST XTAL2
P0[1]/RXD0/PWM3/EINT0 P1[28]/TDI
P0[2]/SCL/CAP0[0] V
SSA
V
DD(3V3)
V
SSA(PLL)
P1[26]/RTCK RESET
V
SS
P1[29]/TCK
P0[3]/SDA/MAT0[0]/EINT1 P0[20]/MAT1[3]/SSEL1/EINT3
P0[4]/SCK0/CAP0[1] P0[19]/MAT1[2]/MOSI1/CAP1[2]
P1[25]/EXTIN0 P0[18]/CAP1[3]/MISO1/MAT1[3]
P0[5]/MISO0/MAT0[1] P1[30]/TMS
P0[6]/MOSI0/CAP0[2] V
DD(3V3)
P0[7]/SSEL0/PWM2/EINT2 V
SS
P1[24]/TRACECLK V
DD(1V8)
002aad176
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
LPC2114_2124 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 10 June 2011 6 of 42
NXP Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
5.2 Pin description
Table 3. Pin description
Symbol Pin Type Description
P0[0] to P0[31] I/O Port 0 is a 32-bit bidirectional I/O port with individual direction controls for each bit.
The operation of port 0 pins depends upon the pin function selected via the Pin
Connect Block. Pins 26 and 31 of port 0 are not available.
P0[0]/TXD0/
PWM1
19 O TXD0 — Transmitter output for UART0.
O PWM1 — Pulse Width Modulator output 1.
P0[1]/RXD0/
PWM3/EINT0
21 I RXD0 — Receiver input for UART0.
O PWM3 — Pulse Width Modulator output 3.
I EINT0 — External interrupt 0 input
P0[2]/SCL/
CAP0[0]
22 I/O SCL — I
2
C-bus clock input/output. Open-drain output (for I
2
C-bus compliance).
I CAP0[0] — Capture input for Timer 0, channel 0.
P0[3]/SDA/
MAT0[0]/EINT1
26 I/O SDA — I
2
C-bus data input/output. Open-drain output (for I
2
C-bus compliance).
O MAT0[0] — Match output for Timer 0, channel 0.
I EINT1 — External interrupt 1 input.
P0[4]/SCK0/
CAP0[1]
27 I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.
I CAP0[1] — Capture input for Timer 0, channel 1.
P0[5]/MISO0/
MAT0[1]
29 I/O MISO0 — Master In Slave OUT for SPI0. Data input to SPI master or data output
from SPI slave.
O MAT0[1] — Match output for Timer 0, channel 1.
P0[6]/MOSI0/
CAP0[2]
30 I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data input
to SPI slave.
I CAP0[2] — Capture input for Timer 0, channel 2.
P0[7]/SSEL0/
PWM2/EINT2
31 I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.
O PWM2 — Pulse Width Modulator output 2.
I EINT2 — External interrupt 2 input.
P0[8]/TXD1/
PWM4
33 O TXD1 — Transmitter output for UART1.
O PWM4 — Pulse Width Modulator output 4.
P0[9]/RXD1/
PWM6/EINT3
34 I RXD1 — Receiver input for UART1.
O PWM6 — Pulse Width Modulator output 6.
I EINT3 — External interrupt 3 input.
P0[10]/RTS1/
CAP1[0]
35 O RTS1 — Request to Send output for UART1.
I CAP1[0] — Capture input for Timer 1, channel 0.
P0[11]/CTS1/
CAP1[1]
37 I CTS1 — Clear to Send input for UART1.
I CAP1[1] — Capture input for Timer 1, channel 1.
P0[12]/DSR1/
MAT1[0]
38 I DSR1 — Data Set Ready input for UART1.
O MAT1[0] — Match output for Timer 1, channel 0.
P0[13]/DTR1/
MAT1[1]
39 O DTR1 — Data Terminal Ready output for UART1.
O MAT1[1] — Match output for Timer 1, channel 1.
P0[14]/DCD1/
EINT1
41 I DCD1
Dat
a Carrier Detect input for UART1.
I EINT1 — External interrupt 1 input.
Note: LOW on this pin while RESET
is LOW forces on-chip bootloader to take
control of the part after reset.

LPC2124FBD64/01,15

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 256KF/16KR/I2C
Lifecycle:
New from this manufacturer.
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