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TDA7467
I
2
C BUS INTERFACE
Data transmission from microprocessor to the TDA7467 and vice versa takes place through the 2 wires
I
2
C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
Data Validity
As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and Stop Conditions
As shown in fig.2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
Acknowledge
The master (µP) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
3). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply
it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 1. Data Validity on the I
2
CBUS
Figure 2. Timing Diagram of I
2
CBUS
Figure 3. Acknowledge on the I
2
CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
SCL
SDA
START
I
2
CBUS
STOP
D99AU1032
SCL
1
MSB
23789
SDA
START
ACKNOWLEDGMENT
FROM RECEIVER
D99AU1033
