AD7680
Rev. A | Page 3 of 24
SPECIFICATIONS
1
Table 2. V
DD
= 4.5 V to 5.5 V, f
SCLK
= 2.5 MHz, f
SAMPLE
= 100 kSPS, unless otherwise noted; T
A
= T
MIN
to T
MAX
, unless otherwise noted
Parameter A, B Versions
1
Unit Test Conditions/Comments
DYNAMIC PERFORMANCE f
IN
= 10 kHz sine wave
Signal-to-Noise + Distortion (SINAD)
2
83 dB min
85 dB typ
Signal-to-Noise Ratio (SNR)
2
84 dB min
86 dB typ
Total Harmonic Distortion (THD)
2
−97 dB typ
Peak Harmonic or Spurious Noise (SFDR)
2
−95 dB typ
Intermodulation Distortion (IMD)
2
Second-Order Terms −94 dB typ
Third-Order Terms −100 dB typ
Aperture Delay 20 ns max
Aperture Jitter 30 ps typ
Full Power Bandwidth 8 MHz typ @ −3 dB
2.2 MHz typ @ −0.1 dB
DC ACCURACY
No Missing Codes 15 Bits typ
Integral Nonlinearity
2
±4 LSB typ
Offset Error
2
±1.68 mV max
Gain Error
2
±0.038 % FS max
ANALOG INPUT
Input Voltage Ranges 0 to V
DD
V
DC Leakage Current ±0.3 μA max
Input Capacitance 30 pF typ
LOGIC INPUTS
Input High Voltage, V
INH
2.8 V min
Input Low Voltage, V
INL
0.4 V max
Input Current, I
IN
±0.3 μA max Typically 10 nA, V
IN
= 0 V or V
DD
Input Capacitance, C
IN
2, 3
10 pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DD
− 0.2 V min I
SOURCE
= 200 μA
Output Low Voltage, V
OL
0.4 V max I
SINK
= 200 μA
Floating-State Leakage Current ±0.3 μA max
Floating-State Output Capacitance
2, 3
10 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 8 μs max 20 SCLK cycles with SCLK at 2.5 MHz
9.6 μs max 24 SCLK cycles with SCLK at 2.5 MHz
Track-and-Hold Acquisition Time 1.5 μs max
400 ns max Sine wave input ≤ 10 kHz
Throughput Rate 100 kSPS See the Serial Interface section
POWER REQUIREMENTS
V
DD
4.5/5.5 V min/V max
I
DD
Digital I/P
S
= 0 V or V
DD
Normal Mode (Static) 5.2 mA max SCLK on or off. V
DD
= 5.5 V
Normal Mode (Operational) 4.8 mA max f
SAMPLE
= 100 kSPS. V
DD
= 5.5 V; 3.3 mA typ
Full Power-Down Mode 0.5 μA max SCLK on or off. V
DD
= 5.5 V
Power Dissipation
4
V
DD
= 5.5 V
Normal Mode (Operational) 26.4 mW max f
SAMPLE
= 100 kSPS
Full Power-Down 2.75 μW max
1
Temperature range as follows: B Version: −40°C to +85°C.
2
See the Terminology section.
3
Sample tested during initial release to ensure compliance.
4
See the Power vs. Throughput Rate section.
AD7680
Rev. A | Page 4 of 24
SPECIFICATIONS
1
Table 3. V
DD
= 2.5 V to 4.096 V, f
SCLK
= 2.5 MHz, f
SAMPLE
= 100 kSPS, unless otherwise noted; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Parameter A Version
1
B Version
1
Unit Test Conditions/Comments
DYNAMIC PERFORMANCE f
IN
= 10 kHz sine wave
Signal-to-Noise + Distortion (SINAD)
2
83 83 dB min V
DD
= 4.096 V
82 82 dB min V
DD
= 2.5 V to 3.6 V
86 86 dB typ
Signal-to-Noise Ratio (SNR)
2
84 84 dB min V
DD
= 4.096 V
83 83 dB min V
DD
= 2.5 V to 3.6 V
86 86 dB typ
Total Harmonic Distortion (THD)
2
−98 −98 dB typ
Peak Harmonic or Spurious Noise (SFDR)
2
−95 −99 dB typ
Intermodulation Distortion (IMD)
2
Second-Order Terms −94 −94 dB typ
Third-Order Terms −100 −100 dB typ
Aperture Delay 20 10 ns max
Aperture Jitter 30 30 ps typ
Full Power Bandwidth 7 7 MHz typ @ −3 dB; V
DD
= 4.096 V
5 5 MHz typ @ −3 dB; V
DD
= 2.5 V to 3.6 V
2 2 MHz typ @ −0.1 dB; V
DD
= 4.096 V
1.6 1.6 MHz typ @ −0.1 dB; V
DD
= 2.5 V to 3.6 V
DC ACCURACY
No Missing Codes 14 15 Bits min
Integral Nonlinearity
2
±3.5 ±3.5 LSB max V
DD
= 4.096 V
±3 ±3 LSB max V
DD
= 2.5 V to 3.6 V
Offset Error
2
±1.25 ±1.25 mV max V
DD
= 4.096 V
±1.098 ±1.098 mV max V
DD
= 2.5 V to 3.6 V
Gain Error
2
±0.038 ±0.038 % FS max
ANALOG INPUT
Input Voltage Ranges 0 to V
DD
0 to V
DD
V
DC Leakage Current ±0.3 ±0.3 μA max
Input Capacitance 30 30 pF typ
LOGIC INPUTS
Input High Voltage, V
INH
2.4 2.4 V min
Input Low Voltage, V
INL
0.4 0.4 V max
Input Current, I
IN
±0.3 ±0.3 μA max Typically 10 nA, V
IN
= 0 V or V
DD
Input Capacitance, C
IN
2, 3
10 10 pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DD
− 0.2 V
DD
− 0.2 V min I
SOURCE
= 200 μA
Output Low Voltage, V
OL
0.4 0.4 V max I
SINK
= 200 μA
Floating-State Leakage Current ±0.3 ±0.3 μA max
Floating-State Output Capacitance
2, 3
10 10 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 8 8 μs max 20 SCLK cycles with SCLK at 2.5 MHz
9.6 9.6 μs max 24 SCLK cycles with SCLK at 2.5 MHz
Track-and-Hold Acquisition Time 1.5 1.5 μs max Full-scale step input
400 400 ns max Sine wave input ≤ 10 kHz
Throughput Rate 100 100 kSPS See the Serial Interface section
AD7680
Rev. A | Page 5 of 24
Parameter A Version
1
B Version
1
Unit Test Conditions/Comments
POWER REQUIREMENTS
V
DD
2.5/4.096 2.5/4.096 V min/max
I
DD
Digital I/Ps = 0 V or V
DD
Normal Mode (Static) 2.8 2.8 mA max SCLK on or off; V
DD
= 4.096 V
2 2 mA max SCLK on or off; V
DD
= 3.6 V
Normal Mode (Operational) 2.6 2.6 mA max f
SAMPLE
= 100 kSPS; V
DD
= 4.096 V; 1.75 mA typ
1.9 1.9 mA max f
SAMPLE
= 100 kSPS; V
DD
= 3.6 V; 1.29 mA typ
Full Power-Down Mode 0.3 0.3 μA max SCLK on or off
Power Dissipation
4
Normal Mode (Operational) 10.65 10.65 mW max f
SAMPLE
= 100 kSPS; V
DD
= 4.096 V
6.84 6.84 mW max f
SAMPLE
= 100 kSPS; V
DD
= 3.6 V
3 3 mW typ V
DD
= 2.5 V
Full Power-Down 1.23 1.23 μW max V
DD
= 4.096V
1.08 1.08 μW max V
DD
= 3.6 V
1
Temperature range as follows: A, B Versions: −40°C to +85°C.
2
See the Terminology section.
3
Sample tested during initial release to ensure compliance.
4
See the Power vs. Throughput Rate section.

AD7680BRMZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3mW 100kSPS 16-Bit
Lifecycle:
New from this manufacturer.
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