MAX1937/MAX1938/MAX1939
Two-Phase Desktop CPU Core Supply
Controllers with Controlled VID Change
16 ______________________________________________________________________________________
MOSFET Drivers
The DH_ and DL_ drivers are optimized for driving large
high-side (N1 and N2) and larger low-side MOSFETs
(N3 and N4). This is consistent with the low duty-cycle
operation of the controller. The DL_ low-side drive wave-
form is always the complement of the DH_ high-side
drive waveform, with a fixed dead-time between one
MOSFET turning off and the other turning on to prevent
cross-conduction or shoot-through current.
The internal transistor that drives DL_ low is robust with
a 0.5Ω (typ) on-resistance. This helps prevent DL_ from
being pulled up during the fast rise time of the LX_
node due to capacitive coupling from the drain to the
gate of the low-side synchronous-rectifier MOSFET.
However, some combinations of high-side and low-side
MOSFETs may cause excessive gate-drain coupling,
leading to poor efficiency, EMI, and shoot-through cur-
rents. This is often remedied by adding a resistor (typi-
cally less than 5Ω) in series with BST_, which increases
the turn-on time of the high-side MOSFET without
degrading the turn-off time.
Current-Limit Circuit
The MAX1937/MAX1938/MAX1939 use either the on-
resistance of the low-side MOSFETs or a current-sense
resistor to monitor the inductor current. Using the low-
side MOSFETs’ on-resistance as the current-sense ele-
ment provides a lossless and inexpensive solution ideal
for high-efficiency or cost-sensitive applications. The dis-
advantage to this method is that the on-resistance of
MOSFETs vary from part to part, and overtemperature,
which means it cannot be counted on for high accuracy.
If high accuracy is needed, use current-sense resistors,
which provide an accurate current limit under all condi-
tions but reduce efficiency slightly because of the power
lost in the resistors.
The current-limit circuit employs a “valley” current-
sensing algorithm to monitor the inductor current. If the
current-sense signal does not drop below the current-
limit threshold, the controller does not initiate a new
cycle. This limits the maximum value of I
VALLEY
to the
current set by the current-limit threshold (Figure 2).
The current-limit threshold is adjustable over a wide
range, allowing for a range of current-sense resistor
values. The voltage on ILIM sets the current-limit
threshold between PGND and CS_ to 0.1
✕
V
ILIM
. The
10mV to 200mV adjustment range corresponds to ILIM
voltages from 100mV to 2V. The ILIM voltage is set by a
resistor-divider between REF and GND. See the Setting
the Current Limit section for details.
Current Balancing
The DC current balancing between phases depends on
the accuracy of the current-sense elements and the off-
set of the current-balance amplifier.
The maximum offset of the current-balance amplifier
(V
CBOFFSET
) is ±3mV. The current-balance accuracy
can be calculated from:
Current-balance accuracy = V
CBOFFSET
/ (I
L
✕
R
CS
)
where I
L
is the peak inductor current and R
CS
is the
value of the current-sense resistor.
The current-balance accuracy is most important at full
load. With a load current of 50A (I
L
= 25A) and 2mΩ
current-sense resistors, the worst-case current-balance
accuracy is:
Current-balance accuracy = 0.003 / (25
✕
0.002) = 6%
If the on-resistance of the low-side MOSFETs is used
for current sensing, the part-to-part variation of the
MOSFET on-resistance is a significant factor in the cur-
rent balance. The matching between MOSFETs should
be on the order of 15%, worst case. Thus, even if the
current-balance amplifier has no offset, the DC-current
balance could be as bad as 15%. In practice, a little
help is received from the thermal ballasting of the
MOSFETs. That is to say, the positive temperature coef-
ficient of the on-resistance of MOSFETs reduces the
mismatch current between the two phases.
Voltage Positioning (VPOS)
During a load transient, the output voltage instantly
changes by the ESR of the output capacitors times the
change in load current (ΔV
OUT
= -ESR
COUT
✕
ΔI
LOAD
).
Conventional DC-DC converters respond by regulating
the output voltage back to its nominal state after the
load transient occurs (Figure 3). However, the CPU
requires that the output voltage remain within a specific
voltage band. Dynamically positioning the output volt-
age allows the use of fewer output capacitors and
reduces power consumption under heavy load.
For a conventional (nonvoltage-positioned) circuit, the
total output voltage deviation from light load to full load
and back to light load is:
V
P-P1
= 2
✕
(ESR
COUT
✕
ΔI
LOAD
) + V
SAG
+ V
SOAR
where V
SAG
and V
SOAR
are defined in the Output
Capacitor Selection section. Setting the converter to
regulate at a lower voltage when under load allows a
larger voltage step when the output current suddenly
decreases. The total voltage change for a voltage-posi-
tioned circuit is:
V
P-P2
= (ESR
COUT
✕
ΔI
LOAD
) + V
SAG
+V
SOAR
