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ADA4424-6ARUZ-R7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
ADA4424-6
Rev. C | Page 3 of 16
SPECIFICATIONS
V
DD3
= 3.3 V, T
A
= 25°C, V
O
= 2.042 V p-p, R
L
= 150 Ω, dc-coupled outputs, unless otherwise noted. Charge pump configured as shown in
Figure 18.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
OVERALL PERFORMANCE
DC Voltage Gain All channels 6.0 6.2 6.4 dB
Input Voltage Range, All Inputs Not including dc offset −0.6 to +1.4 V
Output Voltage Range, All Outputs −1.6 to +3.0 V
Input Bias Current Y_IN, HY_IN, dc-coupled 30 pA
Input Impedance C_IN, HPb_IN, HPr_IN, ac-coupled 800 kΩ
Output Resistance
Y_OUT, C_OUT, CVBS_OUT, HY_OUT, HPb_OUT,
HPr_OUT, dc-coupled
0.5 Ω
L1_OUT, L2_OUT, L3_OUT, S1/S2_OUT, dc-coupled 10.5 kΩ
SD CHANNEL DYNAMIC PERFORMANCE
In-Band Peaking f = 100 kHz to 6.75 MHz 0.00 0.01 dB
1 dB Bandwidth 14 18 MHz
Out-of-Band Rejection f = 148.5 MHz 38 42 dB
Crosstalk f = 1 MHz 67 dB
Total Harmonic Distortion f = 1 MHz, V
O
= 1.4 V p-p 0.07 %
Signal-to-Noise Ratio f = 100 kHz to 6 MHz, unweighted 68 dB
Group Delay Variation f = 100 kHz to 5 MHz 1 ns
Differential Gain NTSC 0.2 %
Differential Phase NTSC 0.5 Degrees
ED CHANNEL DYNAMIC PERFORMANCE FC_SEL = low (0)
In-Band Peaking f = 100 kHz to 13.5 MHz 0.02 0.1 dB
1 dB Bandwidth 21 25 MHz
Out-of-Band Rejection f = 148.5 MHz 38 42 dB
Crosstalk f = 1 MHz 65 dB
Total Harmonic Distortion f = 5 MHz, V
O
= 1.4 V p-p 0.45 %
Signal-to-Noise Ratio f = 100 kHz to 13.5 MHz, unweighted 66 dB
Group Delay Variation f = 100 kHz to 13.5 MHz 1.5 ns
HD CHANNEL DYNAMIC PERFORMANCE FC_SEL = high (1)
In-Band Peaking f = 100 kHz to 30 MHz 0.1 0.2 dB
1 dB Bandwidth Y Channel (HY_OUT) 30 39 MHz
P Channels (HPb_OUT, HPr_OUT) 25 34 MHz
Out-of-Band Rejection f = 148.5 MHz 33 37 dB
Crosstalk f = 1 MHz 65 dB
Total Harmonic Distortion f = 10 MHz, V
O
= 1.4 V p-p 1.2 %
Signal-to-Noise Ratio f = 100 kHz to 30 MHz, unweighted 65 dB
Group Delay Variation f = 100 kHz to 30 MHz 2.2 ns
DC CHARACTERISTICS
Operating Voltage, 3.3 V Supply 3.14 to 3.46 V
Quiescent Supply Current, 3.3 V Supply
Both active, SD_ENABLE = high, HD_ENABLE = high,
no load, no signal, not including D/S terminal outputs
93 133 mA
SD disabled, SD_ENABLE = low, HD_ENABLE = high 54 mA
HD disabled, SD_ENABLE = high, HD_ENABLE = low 45 mA
Both disabled, SD_ENABLE = low, HD_ENABLE = low 6.1 10 mA
Operating Voltage, 5 V Supply 4.75 to 5.25 V
ADA4424-6
Rev. C | Page 4 of 16
Parameter Test Conditions/Comments Min Typ Max Unit
Quiescent Supply Current, 5 V Supply
SD_ENABLE = high, HD_ENABLE = high,
R
L
= 100 kΩ, D1, D2, D3 = high, S = high
190 200 μA
SD_ENABLE = low, HD_ENABLE = low 5 15 μA
PSRR ED/HD channels, output referred −42 dB
SD channels, output referred −41 dB
DC Offset See Table 6 and Table 7
Input Referred, Offset Cancellation
Disabled Mode
OFFSET_ENB = low
SD Channels Y_IN = 0 V dc −60 −20 +60 mV
CVBS Channel Y_IN = 0 V dc −100 −40 +100 mV
ED/HD Channels HY_IN = 0 V dc −60 −20 +60 mV
Input Referred, Fixed Offset
Cancellation Mode
OFFSET_ENB = high, MODE1 = high
SD Fixed High Offset Mode Y_IN = 1.0 V dc, MODE0 = low −100 −30 +100 mV
ED/HD Fixed High Offset Mode HY_IN = 1.1 V dc, MODE0 = low −100 −38 +100 mV
SD Fixed Low Offset Mode Y_IN = 0.33 V dc, MODE0 = high −90 −17 +90 mV
ED/HD Fixed Low Offset Mode HY_IN = 0.33 V dc, MODE0 = high −100 −25 +100 mV
Input Referred, Auto Offset
Cancellation Mode
OFFSET_ENB = high, MODE1 = low
SD Auto Offset Mode
Sync Tip Sampling
Y_IN = 0 V to 1.0 V dc, MODE0 = low −70 −36 +70 mV
ED/HD Auto Offset Mode
Sync Tip Sampling
HY_IN = 0 V to 1.1 V dc, MODE0 = low −95 −46 +95 mV
SD Auto Offset Mode
Back Porch Sampling
Y_IN = 0 V to 1.0 V dc, MODE0 = high −25 −6 +25 mV
ED/HD Auto Offset Mode
Back Porch Sampling
HY_IN = 0 V to 1.1 V dc, MODE0 = high −25 −5 +25 mV
FC_SEL Input Logic Low Level 0 0.6 V
FC_SEL Input Logic High Level 1.2 V
DD3
V
xD_ENABLE, OFFSET_ENB, MODEx
Input Logic Low Level
0 0.8 V
xD_ENABLE, OFFSET_ENB, MODEx
Input Logic High Level
2.0 V
DD3
V
xD_ENABLE Assert Time xD_ENABLE = low to high 95 ns
xD_ENABLE Deassert Time xD_ENABLE = high to low 20 ns
xD_ENABLE Input Bias Current Disabled, xD_ENABLE = low 6.1 μA
Input-to-Output Isolation Disabled, xD_ENABLE = low, f = 5 MHz −100 dB
D- and S-Terminal Input Logic
Low Level
R
L
= 100 kΩ 0 0.6 V
D- and S-Terminal Input Logic
Mid Level
R
L
= 100 kΩ 0.9 1.9 V
D- and S-Terminal Input Logic
High Level
R
L
= 100 kΩ 2.7 V
DD3
V
D- and S-Terminal Input Logic Open
(Hi-Z) Resistance Value
R
L
= 100 kΩ 200 kΩ
D-Terminal (L1_OUT, L2_OUT, L3_OUT)
Low Level Output
V
DD5
= 5.0 V, R
L
= 100 kΩ, D1, D2, D3 = low 0.0 V
D-Terminal (L1_OUT, L3_OUT) Mid
Level Output
V
DD5
= 5.0 V, R
L
= 100 kΩ, D1, D3 = mid or open 2.1 V
D-Terminal (L1_OUT, L2_OUT, L3_OUT)
High Level Output
V
DD5
= 5.0 V, R
L
= 100 kΩ, D1, D2, D3 = high 4.5 V
S-Terminal (S1/S2_OUT) Low Level
Output
V
DD5
= 5.0 V, R
L
= 100 kΩ, S = low 0.0 V
ADA4424-6
Rev. C | Page 5 of 16
Parameter Test Conditions/Comments Min Typ Max Unit
S-Terminal (S1/S2_OUT) Mid Level
Output
V
DD5
= 5.0 V, R
L
= 100 kΩ, S = mid or open 2.1 V
S-Terminal (S1/S2_OUT) High Level
Output
V
DD5
= 5.0 V, R
L
= 100 kΩ, S = high 4.5 V
CHARGE PUMP CHARACTERISTICS
All channels operating; C1 = C2 = 4.7 μF, C3 = C4 =
1.0 μF, R1 = 1 Ω (see Figure 18)
Output Voltage −1.66 V
Output Voltage Ripple 180 mV p-p
Output Ripple Frequency 100 kHz
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ADA4424-6ARUZ-R7

Mfr. #:
Buy ADA4424-6ARUZ-R7
Manufacturer:
Analog Devices Inc.
Description:
Video ICs 6 CHl SD/ED/HD Video Filter Charge Pump
Lifecycle:
New from this manufacturer.
Delivery:
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