3
Integrated
Circuit
Systems, Inc.
ICS932S421C
1460E—08/25/09
Pin Description (Continued)
Pin # PIN NAME T
pe Pin Description
29 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
30 SDATA I/O Data pin for SMBus circuitry, 3.3V tolerant.
31 Vtt_PwrGd#/PD IN
Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to
be sampled. PD is an asynchronous active high input pin used to put the device into a
low power state. The internal clocks, PLLs and the crystal oscillator are stopped.
32 NC N/A No Connection.
33 IREF OUT
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
34 GNDA PWR Ground pin for the PLL core.
35 VDDA PWR 3.3V power for the PLL core.
36 CPUCLKC3 OUT
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
37 CPUCLKT3 OUT
True clock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
38 VDDCPU PWR Supply for CPU clocks, 3.3V nominal
39 CPUCLKC2 OUT
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
40 CPUCLKT2 OUT
True clock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
41 GNDCPU PWR Ground pin for the CPU outputs
42 CPUCLKC1 OUT
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
43 CPUCLKT1 OUT
True clock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
44 VDDCPU PWR Supply for CPU clocks, 3.3V nominal
45 CPUCLKC0 OUT
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
46 CPUCLKT0 OUT
True clock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
47 VDDCPU PWR Supply for CPU clocks, 3.3V nominal
48 FS_A IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics
for Vil_FS and Vih_FS values.
49 FS_B/TEST_MODE IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics
for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z
and REF/N divider mode while in test mode. Refer to Test Clarification Table.
50 GNDREF PWR Ground pin for the REF outputs.
51 X2 OUT Crystal output, Nominally 14.318MHz
52 X1 IN Crystal input, Nominally 14.318MHz.
53 VDDREF PWR Ref, XTAL power supply, nominal 3.3V
54 REF1 OUT 14.318 MHz reference clock.
55 REF0 OUT 14.318 MHz reference clock.
56 FS_C/TEST_SEL IN
3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see
input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table