6
Integrated
Circuit
Systems, Inc.
ICS932S421C
1460E—08/25/09
Absolute Maximum Rating
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
3.3V Core Supply Voltage VDD_A
-
V
DD
+ 0.5V V
1
3.3V Logic Input Supply
Voltage
VDD_In
-
GND - 0.5 V
DD
+ 0.5V V
1
Storage Temperature Ts
-
-65 150
°
C
1
Ambient Operating Temp Tambient
-
070°C
1
Case Temperature Tcase
-
115 °C
1
Input ESD protection HBM ESD prot
-
2000 V
1
1
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS Notes
Input High Voltage V
IH
3.3 V +/-5% 2 V
DD
+ 0.3 V 1
Input Low Voltage V
IL
3.3 V +/-5% V
SS
- 0.3 0.8 V 1
Input High Current I
IH
V
IN
= V
DD
-5 5 uA 1
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
-5 uA 1
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200 uA 1
Low Threshold Input-
High Voltage
V
IH_FS
3.3 V +/-5% 0.7 V
DD
+ 0.3 V 1
Low Threshold Input-
Low Voltage
V
IL_FS
3.3 V +/-5% V
SS
- 0.3 0.35 V 1
Operating Supply Current I
DD3.3OP
Full Active, C
L
= Full load; 350 mA 1
all diff pairs driven 70 mA 1
all differential pairs tri-stated 12 mA 1
Input Frequency F
i
V
DD
= 3.3 V 14.31818 MHz 2
Pin Inductance L
in
7nH1
C
IN
Logic Inputs 5 pF 1
C
OU
Output pin capacitance 6 pF 1
C
INX
X1 & X2 pins 5 pF 1
Clk Stabilization T
STAB
From VDD Power-Up or de-
assertion of PD to 1st clock
1.8 ms 1
Modulation Frequency Triangular Modulation 30 33 kHz 1
Tdrive_PD
CPU output enable after
PD de-assertion
300 us 1
Tfall_PD PD fall time of 5 ns 1
Trise_PD PD rise time of 5 ns 1
SMBus Voltage V
D
2.7 5.5 V 1
Low-level Output Voltage V
OL
@ I
PULLUP
0.4 V 1
Current sinking at
V
OL
= 0.4 V
I
PULLUP
4mA1
SCLK/SDATA
Clock/Data Rise Time
T
RI 2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000 ns 1
SCLK/SDATA
Clock/Data Fall Time
T
FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300 ns 1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1
Guaranteed by design and characterization, not 100% tested in production.
2
Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
Input Low Current
Powerdown Current I
DD3. 3PD
Input Capacitance
