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MC100E210FNG

P1-P3P4-P6P7-P8
MC100E210
http://onsemi.com
4
AC CHARACTERISTICS V
CCx
= 5.0 V; V
EE
= 0.0 V or V
CCx
= 0.0 V; V
EE
= −5.0 V (Note 8)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
f
MAX
Maximum Toggle Frequency 700 700 700 MHz
t
PLH
t
PHL
Propagation Delay to Output
IN (differential) (Note 9)
IN (single−ended) (Note 10)
475
400
675
700
500
450
700
750
500
450
700
750
ps
t
skew
Within−Device Skew Qa to Qb
Qa to Qa,Qb to Qb
Part−to−Part Skew (Differential) (Note 11)
50
50
75
75
200
50
30
75
50
200
50
30
75
50
200
ps
t
JITTER
Random Clock Jitter (RMS) < 1 < 1 < 1 ps
V
PP
Input Voltage Swing (Differential Configuration)
(Note 12)
500 500 500 mV
t
r
/ t
f
Output Rise/Fall Time (20%−80%) 200 600 200 600 200 600 ps
8. V
EE
can vary −0.46 V / +0.8 V.
9. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
10.The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
11. The within−device skew is defined as the worst case difference between any two similar delay paths within a single device.
12.V
PP
(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The V
PP
(min) is AC limited
for the E210 as a differential input as low as 50 mV will still produce full ECL levels at the output.
MC100E210
http://onsemi.com
5
Figure 1. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
50
50
V
TT
Q D
V
TT
= V
CC
− 2.0 V
Resource Reference of Application Notes
AN1404 − ECLinPS Circuit Performance at Non−Standard V
IH
Levels
AN1405 − ECL Clock Distribution Techniques
AN1406 − Designing with PECL (ECL at +5.0 V)
AN1503 − ECLinPS I/O SPICE Modeling Kit
AN1504 − Metastability and the ECLinPS Family
AN1568 − Interfacing Between LVDS and ECL
AN1596 − ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650 − Using Wire−OR Ties in ECLinPS Designs
AN1672 − The ECL Translator Guide
AND8001 − Odd Number Counters Design
AND8002 − Marking and Date Codes
AND8020 − Termination of ECL Logic Devices
MC100E210
http://onsemi.com
6
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
0.007 (0.180)
TL
−M
S
N
SM
0.007 (0.180)
TL
−M
S
N
SM
0.007 (0.180)
TL
−M
S
N
SM
0.010 (0.250)
TL
−M
S
N
SS
0.007 (0.180)
TL
−M
S
N
SM
0.010 (0.250)
TL
−M
S
N
SS
0.007 (0.180)
TL
−M
S
N
SM
0.007 (0.180)
TL
−M
S
N
SM
0.004 (0.100)
SEATING
PLANE
-T-
12.32
12.32
4.20
2.29
0.33
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
2°
10.42
1.02
12.57
12.57
4.57
2.79
0.48
0.81
11.58
11.58
1.21
1.21
1.42
0.50
10°
10.92

1.27 BSC
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
VIEW S
B
U
Z
G1
X
VIEW D-D
H
K
F
VIEW S
G
C
Z
A
R
E
J
0.485
0.485
0.165
0.090
0.013
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
2°
0.410
0.040
0.495
0.495
0.180
0.110
0.019
0.032
0.456
0.456
0.048
0.048
0.056
0.020
10°
0.430

0.050 BSC
-N-
Y BRK
D
D
W
-M-
-L-
28 1
V
G1
K1
P1-P3P4-P6P7-P8

MC100E210FNG

Mfr. #:
Buy MC100E210FNG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 5V ECL Dual 1:4 1:5 Diff Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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