www.irf.com 1
04/30/09
IRF6716MPbF
IRF6716MTRPbF
Fig 1. Typical On-Resistance vs. Gate Voltage
Typical values (unless otherwise specified)
Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage
Click on this section to link to the appropriate technical paper.
Click on this section to link to the DirectFET Website.
Surface mounted on 1 in. square Cu board, steady state.
T
C
measured with thermocouple mounted to top (Drain) of part.
Repetitive rating; pulse width limited by max. junction temperature.
Starting T
J
= 25°C, L = 0.65mH, R
G
= 25Ω, I
AS
= 32A.
Notes:
DirectFET ISOMETRIC
Description
The IRF6716MPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFET
TM
packaging to achieve
the lowest on-state resistance in a package that has the footprint of a SO-8 and only 0.6 mm profile. The DirectFET package is compatible
with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering
techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows
dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%.
The IRF6716MPbF balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and
switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of
processors operating at higher frequencies. The IRF6716MPbF has been optimized for parameters that are critical in synchronous buck
including Rds(on), gate charge and Cdv/dt-induced turn on immunity. The IRF6716MPbF offers particularly low Rds(on) and high Cdv/dt
immunity for synchronous FET applications.
MX
0 102030405060
Q
G
Total Gate Charge (nC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
V
G
S
,
G
a
t
e
-
t
o
-
S
o
u
r
c
e
V
o
l
t
a
g
e
(
V
)
V
DS
= 20V
V
DS
= 13V
I
D
= 32A
Absolute Maximum Ratin
s
Parameter Units
V
DS
Drain-to-Source Voltage V
V
GS
Gate-to-Source Voltage
I
D
@ T
A
= 25°C
Continuous Drain Current, V
GS
@ 10V
I
D
@ T
A
= 70°C
Continuous Drain Current, V
GS
@ 10V
A
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
I
DM
Pulsed Drain Current
E
AS
Single Pulse Avalanche Energy mJ
I
AR
Avalanche Current A
32
Max.
31
180
320
±20
25
39
330
V
DSS
V
GS
R
DS(on)
R
DS(on)
25V max ±20V max
1.2mΩ@10V 2.0mΩ@ 4.5V
Q
g tot
Q
gd
Q
gs2
Q
rr
Q
oss
V
gs(th)
39nC 12nC 5.3nC 28nC 27nC 1.9V
2 3 4 5 6 7 8 9 10
V
GS,
Gate -to -Source Voltage (V)
0
1
2
3
4
5
6
T
y
p
i
c
a
l
R
D
S
(
o
n
)
(
m
Ω
)
I
D
= 40A
T
J
= 25°C
T
J
= 125°C
SQ SX ST MQ
MX
MT MP
Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details)
DirectFET Power MOSFET
l RoHs Compliant and Halogen Free
l Low Profile (<0.6 mm)
l Dual Sided Cooling Compatible
l Ultra Low Package Inductance
l Optimized for High Frequency Switching
l Ideal for CPU Core DC-DC Converters
l Optimized for Sync. FET socket of Sync. Buck Converter
l Low Conduction and Switching Losses
l Compatible with existing Surface Mount Techniques
l 100% Rg tested
PD - 97274C
