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NCP1377BDR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
NCP1377, NCP1377B
www.onsemi.com
7
0
10
20
30
40
50
60
TEMPERATURE (°C)
R
int
k
W
Figure 15. DMG Pin Internal Resistance versus
Temperature
−50 −30 −10 10 30 50 70 90 110 13
0
APPLICATION INFORMATION
INTRODUCTION
The NCP1377 implements a standard current mode
architecture where the switch−off time is dictated by the
peak current setpoint, whereas the core reset detection
triggers the turn−on event. This component represents the
ideal candidate where low part−count is the key parameter,
particularly in low−cost AC−DC adapters, consumer
electronics, auxiliary supplies, etc. Due to its high−
performance high−voltage technology, the NCP1377
incorporates all the necessary components/features needed
to build a rugged and reliable Switchmode Power Supply
(SMPS):
• Transformer Core Reset Detection: Borderline/critical
operation is ensured whatever the operating conditions
are. As a result, there are virtually no primary switch
turn−on losses and no secondary diode recovery
losses. The converter also stays a first−order system
and accordingly eases the feedback loop design.
• Quasi−Resonant Operation: By delaying the turn−on
event, it is possible to restart the MOSFET in the
minimum of the drain−source wave, ensuring reduced
EMI/video noise perturbations. In nominal power
conditions, the NCP1377 operates in Borderline
Conduction Mode (BCM) also called Critical
Conduction Mode.
• Undervoltage Lockout (UVLO): When Vcc falls below
V
CCoff
pulses are stopped and the IC consumption
drops down to a few hundred of mA. When Vcc
reaches the latchoff level (5.6 V typical), the startup
current source is activated and brings Vcc back to
Vcc
on
where the IC attempts to startup.
• Overvoltage Protection (OVP): By sampling the
plateau voltage on the demagnetization winding, the
NCP1377 goes into latched fault condition whenever
an overvoltage condition is detected. The controller
stays fully latched in this position until the Vcc is
cycled down to 4.0 V, e.g. when the user unplugs the
power supply from the mains outlet and replugs it.
• External Latch Trip Point: By externally forcing a
level on the OVP greater than the internal setpoint, it
is possible to latchoff the IC, e.g. with a signal coming
from a temperature sensor.
• Adjustable Skip Cycle Level: By offering the ability
to tailor the level at which the skip cycle takes place,
the designer can make sure that the skip operation
only occurs at low peak current. This point guarantees
a noise−free operation with cheap transformer. This
option also offers the ability to fix the maximum
switching frequency when entering light load conditions.
• Overcurrent Protection (OCP): NCP1377 enters burst
mode as soon as the power supply undergoes an
overload which is detected through the sense of the
auxiliary voltage. As detailed above, as soon as Vcc
crosses the undervoltage lockout level (VCCoff in the
electrical table), all pulses are stopped and the device
enters a safe low power operation which prevents from
any lethal thermal runaway. By monitoring the Vcc
level, the startup current source is activated ON and
OFF to create a kind of burst mode where the SMPS
tries to restart. If the fault has gone, the SMPS
resumes operation. On the other hand, if the fault is
still there, the burst sequence starts again.
Startup Sequence
When the power supply is first powered from the mains
outlet, the internal current source (typically 4.0 mA) is
biased and charges up the Vcc capacitor. When the voltage
on this Vcc capacitor reaches the Vcc
ON
level (typically
12.5 V), the current source turns off and no longer wastes
any power. At this time, the Vcc capacitor only supplies the
controller and the auxiliary supply is supposed to take over
before Vcc collapses below V
CCoff
. Figure 16 shows the
internal arrangement of this structure.
−
+
Vcc
ON
/Vcc
OFF
8 HV
IC1 or 0
6
4
CV
CC Au
x
Figure 16. The Current Source Brings Vcc Above
Vcc
ON
and Then Turns Off
NCP1377, NCP1377B
www.onsemi.com
8
Once the power supply has started, the V
CC
shall be
constrained below 18 V, which is the maximum rating on
pin 6. Figure 17 portrays a typical NCP1377 startup
sequence with a Vcc regulated at 12.5 V.
Figure 17. A Typical Startup Sequence
for the NCP1377
9.50
10.5
11.5
12.5
13.5
12.5 V
Regulation
V
CC
Skipping Cycle Mode
The NCP1377 automatically skips switching cycles
when the output power demand drops below a given level.
This is accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 18)
and follows the following formula:
1
2
·Lp·Ip
2
·Fsw·D
burst
with:
Lp = Primary inductance
Fsw = Switching frequency within the burst
Ip = Peak current at which skip cycle occurs
D
burst
= Burst width/burst recurrence
Figure 18. The Skip Cycle Takes Place at Low Peak
Currents which Guarantees Noise−Free Operation
0
300
200
100
MAX PEAK
CURRENT
WIDTH
RECURRENCE
SKIP CYCLE
CURRENT LIMIT
NORMAL CURRENT
MODE OPERATION
CURRENT SENSE SIGNAL (mV)
+
-
RESET
DRIVER
R
sense
R
skip
+
DRIVER = HIGH ? I = 0
DRIVER = LOW ? I = 200 mA
2
3
Figure 19. A Patented Method Allows for Skip
Level Selection via a Series Resistor Inserted in
Series with the Current
The skip level selection is done through a simple resistor
inserted between the current sense input and the sense
element. Everytime the NCP1377 output driver goes low,
a 200 mA source forces a current to flow through the sense
pin (Figure 19): when the driver is high, the current source
is off and the current sense information is normally
processed. As soon as the driver goes low, the current
source delivers 200 mA and develops a ground referenced
voltage across Rskip. If this voltage is below the feedback
voltage, the current sense comparator stays in the low state
and the internal latch can be triggered by the next clock
cycle. Now, if because of a low load mode the feedback
voltage is below Rskip level, then the current sense
comparator permanently resets the latch and the next clock
cycle (given by the demagnetization detection) is ignored:
we are skipping cycles as shown by Figure 18. As soon as
the feedback voltage goes up again, there can be two
situations: the recurrent period is small and a new
demagnetization detection (next wave) signal triggers the
NCP1377. To the opposite, in low output power conditions,
no more ringing waves are present on the drain and the
toggling of the current sense comparator alone initiates a
new cycle start. Figure 20 depicts these two different
situations.
NCP1377, NCP1377B
www.onsemi.com
9
Figure 20. When the primary natural ringing becomes too low, the internal TimeOut
together with the sense comparator initiates a new cycle when FB passes the skip level.
Demag Restart
Current Sense and Timeout Restart
5 ms5 ms
Drain
Signal
Timeout
Signal
Drain
Signal
Timeout
Signal
An optocoupler is generally used to transfer the feedback
information to the FB pin while providing the necessary
isolation. It introduces a limitation in how low the skip
level can be adjusted since an optocoupler cannot pull the
FB voltage below its Vce(sat), which is usually around
150 mV. Therefore, in order to take into account
temperature and process variations, it is not recommended
to set up the skip level below 250 mV, which corresponds
to a minimum resistor Rskip of 420 W. The 150 mV is a
much lower level than what will usually be used (it sets the
peak current when entering skip mode at 5% of the
maximum peak current). If anyway a lower skip threshold
is needed, care must be taken to select an optocoupler with
a Vce(sat) guaranteed to be below the chosen skip level
with enough margin.
Demagnetization Detection
The core reset detection is done by monitoring the
voltage activity on the auxiliary winding. This voltage
features a FLYBACK polarity. The typical detection level
is fixed at 50 mV as exemplified by Figure 21.
Figure 21. Core Reset Detection is Done through
a Dedicated Auxiliary Winding Monitoring
Figure 22. Internal Pad Implementation
POSSIBLE
RESTARTS
50 mV
7.0
5.0
3.0
1.0
−1.0
0 V
DEMAG SIGNAL (V)
TO INTERNAL
COMPARATOR
Au
x
R
esd
R
dem
ESD2 ESD1
4
52
4
1
R
esd
+ R
int
= 28 k
R
int
3
1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

NCP1377BDR2G

Mfr. #:
Buy NCP1377BDR2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers Quasi Resonant Current Mode PWM
Lifecycle:
New from this manufacturer.
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