FPGA Configuration and HPS Booting
The FPGA fabric and HPS in the SoC FPGA must be powered at the same time. You can
reduce the clock frequencies or gate the clocks to reduce dynamic power.
Once powered, the FPGA fabric and HPS can be configured independently thus
providing you with more design flexibility:
• You can boot the HPS independently. After the HPS is running, the HPS can fully or
partially reconfigure the FPGA fabric at any time under software control. The HPS
can also configure other FPGAs on the board through the FPGA configuration
controller.
• Configure the FPGA fabric first, and then boot the HPS from memory accessible to
the FPGA fabric.
Hardware and Software Development
For hardware development, you can configure the HPS and connect your soft logic in
the FPGA fabric to the HPS interfaces using the Platform Designer system integration
tool in the Intel Quartus Prime software.
For software development, the ARM-based SoC FPGA devices inherit the rich software
development ecosystem available for the ARM Cortex-A9 MPCore processor. The
software development process for Intel SoC FPGAs follows the same steps as those for
other SoC devices from other manufacturers. Support for Linux*, VxWorks*, and other
operating systems are available for the SoC FPGAs. For more information on the
operating systems support availability, contact the Intel FPGA sales team.
You can begin device-specific firmware and software development on the Intel SoC
FPGA Virtual Target. The Virtual Target is a fast PC-based functional simulation of a
target development system—a model of a complete development board. The Virtual
Target enables the development of device-specific production software that can run
unmodified on actual hardware.
Dynamic and Partial Reconfiguration
The Intel Arria 10 devices support dynamic and partial reconfiguration. You can use
dynamic and partial reconfiguration simultaneously to enable seamless reconfiguration
of both the device core and transceivers.
Dynamic Reconfiguration
You can reconfigure the PMA and PCS blocks while the device continues to operate.
This feature allows you to change the data rates, protocol, and analog settings of a
channel in a transceiver bank without affecting on-going data transfer in other
transceiver banks. This feature is ideal for applications that require dynamic
multiprotocol or multirate support.
Partial Reconfiguration
Using partial reconfiguration, you can reconfigure some parts of the device while
keeping the device in operation.
Intel
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Arria
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10 Device Overview
A10-OVERVIEW | 2018.04.09
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Arria
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10 Device Overview
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