• Series (R
S
) and parallel (R
T
) on-chip termination (OCT) for all I/O banks with OCT
calibration to limit the termination impedance variation
• On-chip dynamic termination that has the ability to swap between series and
parallel termination, depending on whether there is read or write on a common
bus for signal integrity
• Easy timing closure support using the hard read FIFO in the input register path,
and delay-locked loop (DLL) delay chain with fine and coarse architecture
External Memory Interface
Intel Arria 10 devices offer massive external memory bandwidth, with up to seven 32-
bit DDR4 memory interfaces running at up to 2,400 Mbps. This bandwidth provides
additional ease of design, lower power, and resource efficiencies of hardened high-
performance memory controllers.
The memory interface within Intel Arria 10 FPGAs and SoCs delivers the highest
performance and ease of use. You can configure up to a maximum width of 144 bits
when using the hard or soft memory controllers. If required, you can bypass the hard
memory controller and use a soft controller implemented in the user logic.
Each I/O contains a hardened DDR read/write path (PHY) capable of performing key
memory interface functionality such as read/write leveling, FIFO buffering to lower
latency and improve margin, timing calibration, and on-chip termination.
The timing calibration is aided by the inclusion of hard microcontrollers based on
Intel's Nios
®
II technology, specifically tailored to control the calibration of multiple
memory interfaces. This calibration allows the Intel Arria 10 device to compensate for
any changes in process, voltage, or temperature either within the Intel Arria 10 device
itself, or within the external memory device. The advanced calibration algorithms
ensure maximum bandwidth and robust timing margin across all operating conditions.
In addition to parallel memory interfaces, Intel Arria 10 devices support serial memory
technologies such as the Hybrid Memory Cube (HMC). The HMC is supported by the
Intel Arria 10 high-speed serial transceivers which connect up to four HMC links, with
each link running at data rates up to 15 Gbps.
Related Information
External Memory Interface Spec Estimator
Provides a parametric tool that allows you to find and compare the performance of
the supported external memory interfaces in IntelFPGAs.
Memory Standards Supported by Intel Arria 10 Devices
The I/Os are designed to provide high performance support for existing and emerging
external memory standards.
Intel
®
Arria
®
10 Device Overview
A10-OVERVIEW | 2018.04.09
Intel
®
Arria
®
10 Device Overview
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