AT25128/256
2
in space saving 8-pin PDIP (AT25128/256), 8-pin EIAJ
SOIC (AT25128/256), 8-pin and 16-pin JEDEC SOIC
(AT25128), 14-pin TSSOP (AT25128), 20-pin TSSOP
(AT25128/256), and 8-pin Leadless Array (AT25128/256)
packages. In addition, the entire family is available in 5.0V
(4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V)
versions.
The AT25128/256 is enabled through the Chip Select pin
(CS
) and accessed via a 3-wire interface consisting of
Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK). All programming cycles are completely self-
timed, and no separate ERASE cycle is required before
WRITE.
BLOCK WRITE protection is enabled by programming the
status register with top ¼, top ½ or entire array of write pro-
tection. Separate program enable and program disable
instructions are provided for additional data protection.
Hardware data protection is provided via the WP
pin to pro-
tect against inadvertent write attempts to the status regis-
ter. The HOLD
pin may be used to suspend any serial
communication without resetting the serial sequence.
Block Diagram
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
16384/32768 x 8