ADM1232A
Rev. A | Page 3 of 8
SPECIFICATIONS
V
CC
= full operating range, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
TEMPERATURE RANGE −40 +85 °C T
A
= T
MIN
to T
MAX
.
POWER SUPPLY
Voltage 4.5 5.0 5.5 V
Current 20 50 μA V
IL
, V
IH
= CMOS levels.
200 500 μA V
IL
, V
IH
= TTL levels.
STROBE AND PB RESET INPUTS
Input High Level 2.0 V
CC
+ 0.3 V
Input Low Level −0.3 +0.8 V
INPUT LEAKAGE CURRENT
(STROBE
, TOLERANCE)
−1.0 +1.0 μA
TD 1.6 μA
OUTPUT CURRENT
RESET 8 10 mA When V
CC
is at 4.5 V to 5.5 V.
RESET, RESET
−8 −12 mA When V
CC
is at 4.5 V to 5.5 V.
OUTPUT VOLTAGE
RESET/RESET
V
CC
− 0.5 V
CC
− 0.1 V
While sourcing less than 500 μA, RESET remains within
0.5 V of V
CC
on power-down until V
CC
drops below 2.0 V.
While sinking less than 500 μA, RESET remains within 0.5 V
of GND on power-down until V
CC
drops below 2.0 V.
RESET/RESET High Level
0.4 V
RESET/RESET Low Level
2.4 V
1 V OPERATION
RESET Output Voltage
V
CC
− 0.1 V While sourcing less than 50 μA.
RESET Output Voltage
0.1 V While sinking less than 50 μA.
V
CC
TRIP POINT
5% 4.5 4.62 4.74 V TOLERANCE = GND.
10% 4.25 4.37 4.49 V TOLERANCE = V
CC
.
CAPACITANCE
Input (STROBE, TOLERANCE)
5 pF T
A
= 25°C.
Output (RESET, RESET)
7 pF T
A
= 25°C.
PB RESET
Time 20 ms
PB RESET must be held low for a minimum of 20 ms to
guarantee a reset.
Delay 1 4 20 ms
RESET ACTIVE TIME 250 610 1000
ms
STROBE
Pulse Width 20 ns
Timeout Period 62.5 150 250 ms TD = 0 V.
250 600 1000 ms TD = floating.
500 1200 2000 ms TD = V
CC
.
V
CC
Fall Time 10 μs Guaranteed by design.
Rise Time 0 μs Guaranteed by design.
V
CC
FAIL DETECT TO RESET
OUTPUT DELAY
RESET and RESET Are
Logically Correct 50 μs After V
CC
falls below the set tolerance voltage (see Figure 7).
250 610 1000 ms After V
CC
rises above the set tolerance voltage.
