©2011 Silicon Storage Technology, Inc. DS-25017A 04/11
16
Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Data Sheet
A
Microchip Technology Company
Set Burst
The Set Burst command specifies the number of bytes to be output during a Read Burst command
before the device wraps around. To set the burst length the host drives CE# low, sends the Set Burst
command cycle (C0H) and one data cycle, then drives CE# high. A cycle is two nibbles, or two clocks,
long, most significant nibble first. After power-up or reset, the burst length is set to eight Bytes (00H).
See Table 4 for burst length data and Figure 12 for the sequence.
Figure 12:Set Burst Length Sequence
Read Burst
To execute a Read Burst operation the host drives CE# low, then sends the Read Burst command
cycle (0CH), followed by three address cycles, and then one dummy cycle. Each cycle is two nibbles
(clocks) long, most significant nibble first.
After the dummy cycle, the device outputs data on the falling edge of the SCK signal starting from the
specified address location. The data output stream is continuous through all addresses until termi-
nated by a low-to-high transition on CE#.
During Read Burst, the internal address pointer automatically increments until the last byte of the burst
is reached, then jumps to first byte of the burst. All bursts are aligned to addresses within the burst
length, see Table 5. For example, if the burst length is eight Bytes, and the start address is 06h, the
burst sequence would be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05h, 06h, etc. The pattern would repeat
until the command was terminated by a low-to-high transition on CE#.
During this operation, blocks that are Read-locked will output data 00H.
Table 4: Burst Length Data
Burst Length High Nibble (H0) Low Nibble (L0)
8 Bytes 0h 0h
16 Bytes 0h 1h
32 Bytes 0h 2h
64 Bytes 0h 3h
T4.0 25017
Table 5: Burst Address Ranges
Burst Length Burst Address Ranges
8 Bytes 00-07H, 08-0FH, 10-17H, 18-1FH...
16 Bytes 00-0FH, 10-1FH, 20-2FH, 30-3FH...
32 Bytes 00-1FH, 20-3FH, 40-5FH, 60-7FH...
64 Bytes 00-3FH, 40-7FH, 80-BFH, C0-FFH
T5.0 25017
1359 F32.0
MODE 3 0 1
SCK
SIO(3:0)
CE#
C1 C0
MODE 0
23
H0 L0
MSN
LSN
Note: MSN = Most Significant Nibble,
LSN = Least Significant Nibble
©2011 Silicon Storage Technology, Inc. DS-25017A 04/11
17
Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Data Sheet
A
Microchip Technology Company
Index Jump
Index Jump allows the host to read data using relative addressing instead of absolute addressing; in
some cases this reduces the number of input clocks required to access data. The SST26VF016/032
support three Index Jump options:
Read Page-Index-jump to address index within 256 Byte page
Read Index-jump to address index within 64 KByte block
Read Block-Index - jump to address index in another 64 KByte block.
Index Jumps following a Burst Read command are referenced from the last input address. For exam-
ple, the device initiates a 64-Byte Read Burst instruction from address location 1EH and outputs an
arbitrary number of Bytes. When the device issues a Read Page-Index instruction with 40H as the off-
set, the device will output data from address location 5EH. Index Jump operations following a High
Speed Read (continuous read) instruction are referenced from the last address from which the full byte
of data was output.
Data output by any of the Index-Jump commands follows the pattern of the last non-Index-Jump com-
mand. For example, a Read Page-Index command following a Read Burst, with 64-Byte wrap length,
will continue to deliver data that wraps at 64-Byte boundaries after jumping to the address specified in
the Read Page-Index command.
Read Page-Index (Read PI)
The Read Page-Index (Read PI) instruction increments the address counter within a page of 256
Bytes. To execute a Read PI operation the host drives CE# low then sends the Read PI command
cycle (08H), one address cycle, and one dummy cycle. Each cycle is two nibbles (clocks) long, most
significant nibble first.
The address cycle contain a two’s complement number that specifies the number of bytes and direc-
tion the address pointer will jump. For example, to jump ahead 127 Bytes A1:A0 = 7FH; to jump back
127 Bytes A1:A0 = 81H.
The Read PI command does not cross 256 Byte page boundaries. If the jump distance exceeds the
256 Byte boundary, the address pointer wraps around to the beginning of the page, if the jump is for-
ward, or to the end of the page, if the jump is backward. After the dummy cycle, the device outputs data
on the falling edge of the SCK signal starting from the specified address location.
Read Index
The Read Index (Read I) instruction increments the address counter a specified number of bytes within
a 64 KByte block. To execute a Read I operation the host drives CE# low then sends the Read I com-
mand cycle (09H), two address cycles, and two dummy cycles. Each cycle is two nibbles (clocks) long,
most significant nibble first.
The address cycles contain a two’s complement number that specifies the number of bytes and direc-
tion the address pointer will jump. For example, to jump ahead 256 Bytes, the address cycles would be
0100H; to jump back 256 Bytes, the address cycles would be FF00H.
The Read I command can not cross 64 KByte block boundaries, but it can cross boundaries of smaller
blocks. If the jump distance exceeds the 64 KByte block boundary, the address pointer wraps around
to the beginning of the block, if the jump is forward, and to the end of the block, if the jump is backward.
After the dummy cycles, the device outputs data on the falling edge of the SCK signal starting from the
specified address location.
©2011 Silicon Storage Technology, Inc. DS-25017A 04/11
18
Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Data Sheet
A
Microchip Technology Company
Read Block Index (Read BI)
The Read Block Index (Read BI) instruction increments the address counter a specified number of 64
KByte blocks. To execute a Read BI operation the host drives CE# low, then sends the Read BI com-
mand cycle (10H), one address cycle, and two dummy cycles. Each cycle is two nibbles (clocks) long,
most significant nibble first.
The address cycle contains a two’s complement number specifying the number of blocks and the
direction the address pointer will jump. The least significant address bits, A15:A0, do not change.
After the dummy cycle, the device outputs data on the falling edge of the SCK signal starting from the
specified address location.
JEDEC-ID Read (SPI Protocol)
Using traditional SPI protocol, the JEDEC-ID Read instruction identifies the device as SST26VF016/
032 and the manufacturer as SST. To execute a JECEC-ID operation the host drives CE# low then
sends the JEDEC-ID command cycle (9FH). For SPI modes, each cycle is eight bits (clocks) long,
most significant bit first.
Immediately following the command cycle the device outputs data on the falling edge of the SCK sig-
nal. The data output stream is continuous until terminated by a low-to-high transition on CE#. The
device outputs three bytes of data: manufacturer, device type, and device ID, see Table 6. See Figure
13 for instruction sequence.
Figure 13:JEDEC-ID Sequence (SPI Mode)
Table 6: Device ID Data Output
Product Manufacturer ID (Byte 1)
Device ID
Device Type (Byte 2) Device ID (Byte 3)
SST26VF016 BFH 26H 01H
SST26VF032 BFH 26H 02H
T6.1 25017
26 Device ID
1359 F38.0
CE#
SO
SI
SCK
012345678
HIGH IMPEDANCE
15 1614 28 29 30 31
BF
MODE 3
MODE 0
MSBMSB
9 10111213 1718 32 34
9F
19 20 21 22 23 3324 25 26 27
Note: SIO2 and SIO3 must be driven V
IH

SST26VF016-80-5C-S2AE

Mfr. #:
Manufacturer:
Microchip Technology
Description:
NOR Flash 2.7 to 3.6V 16Mbit Serial Quad I/O Flsh
Lifecycle:
New from this manufacturer.
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