©2011 Silicon Storage Technology, Inc. DS-25017A 04/11
15
Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Data Sheet
Microchip Technology Company
Reset Quad I/O (RSTQIO)
The Reset Quad I/O instruction, FFH, resets the device to 1-bit SPI protocol operation. To execute a
Reset Quad I/O operation, the host drives CE# low, sends the Reset Quad I/O command cycle (FFH)
then, drives CE# high. The device accepts either SPI (8 clocks) or SQI (2 clocks) command cycles. For
SPI, SIO[3:1] are don’t care for this command, but should be driven to V
IH
or V
IL
.
High-Speed Read (80 MHz)
The High-Speed Read instruction, 0BH, is supported in both SPI bus protocol and SQI protocol. On
power-up, the device is set to use SPI.
Initiate High-Speed Read by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and
a dummy byte. CE# must remain active low for the duration of the High-Speed Read cycle. SIO2 and
SIO3 must be driven V
IH
for the duration of the Read cycle. See Figure 10 for the High-Speed Read
sequence for SPI bus protocol.
Figure 10:High-Speed Read Sequence (SPI)
In SQI protocol, the host drives CE# low then send the Read command cycle command, 0BH, followed by
three address cycles and one dummy cycle. Each cycle is two nibbles (clocks) long, most significant nibble first.
After the dummy cycle, the Serial Quad I/O (SQI) Flash Memory outputs data on the falling edge of
the SCK signal starting from the specified address location. The device continually streams data out-
put through all addresses until terminated by a low-to-high transition on CE#. The internal address
pointer automatically increments until the highest memory address is reached, at which point the
address pointer returns to address location 000000H.
During this operation, blocks that are Read-locked will output data 00H.
Figure 11:High-Speed Read Sequence (SQI)
1359 F31.0
CE#
SO/SIO1
SI/SIO0
SCK
ADD.
012345678
ADD. ADD.0B
HIGH IMPEDANCE
15 16 23 24 31 32 39 40
47 48 55 56 63 64
N+2 N+3 N+4
N
N+1
X
MSB
MODE 0
MODE 3
D
OUT
D
OUT
D
OUT
D
OUT
80
71 72
D
OUT
Note: SIO2 and SIO3 must be driven V
IH
1359 F06.2
MODE 3 0 1 2 9 16
CLK
SIO(3:0)
CE#
MODE 3
C1 C0 A5 A4 A3 A2 A1 A0 X X H0 L0 H1 L1 H2 L2 H3 L3
MODE 0MODE 0
MSB
Data OutData In
Note: C[1:0] = 0BH
