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LTC4300A-2CMS8#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LTC4300A-1/LTC4300A-2
4
4300a12fa
–40 25 85
TEMPERATURE (°C)
I
CC
(mA)
4300a12 G01
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
V
CC
= 5.5V
V
CC
= 2.7V
–50 –25 0 25 50 75 100
TEMPERATURE (°C)
I
PULLUPAC
(mA)
4300a12 G03
12
10
8
6
4
2
0
V
CC
= 2.7V
V
CC
= 5V
V
CC
= 3V
TYPICAL PERFORMANCE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
I
PULLUPAC
vs Temperature Connection Circuitry V
OUT
– V
IN
I
CC
vs Temperature (LTC4300A-1)
Input – Output t
PHL
vs
Temperature (LTC4300A-1)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: I
PULLUPAC
varies with temperature and V
CC
voltage, as shown in
the Typical Performance Characteristics section.
Note 3: The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and V
CC
voltage is shown in the Typical Performance
Characteristics section.
Note 4: Guaranteed by design, not subject to test.
Note 5: C
B
= total capacitance of one bus line in pF.
Note 6: These tests measure the difference in high-to-low propagation
delay t
PHL
between the clock and data channels. The delay on each
channel is measured from the 50% point of the falling driven input signal
to the 50% point of the output driven by the LTC4300A-1/LTC4300A-2.
The skew is defined as (t
PHL(SCL)
– t
PHL(SDA)
). Testing is performed in
both directions—from input bus to output bus and vice versa. Tests are
performed with approximately 500pF of distributed equivalent capacitance
on each SDA and SCL pin.
–50 –25 0 25 50 75 100
TEMPERATURE (°C)
t
PHL
(ns)
4300a12 G02
100
80
60
40
20
0
V
CC
= 2.7V
V
CC
= 3.3V
V
CC
= 5.5V
C
IN
= C
OUT
= 100pF
R
PULLUPIN
= R
PULLUPOUT
= 10k
R
PULLUP
(Ω)
0
10,000 20,000 30,000 40,000
V
OUT
– V
IN
(mV)
4300a12 G04
300
250
200
150
100
50
0
V
CC
= 3.3V
V
CC
= 5V
T
A
= 25°C
V
IN
= 0V
LTC4300A-1/LTC4300A-2
5
4300a12fa
PIN FUNCTIONS
ENABLE/V
CC2
(Pin 1): Chip Enable Pin/Card Supply Volt-
age. For the LTC4300A-1, this is a digital CMOS threshold
input pin. Grounding this pin puts the part in a low current
(<1μA) mode. It also disables the rise-time accelerators,
disables the bus precharge circuitry, drives READY low,
isolates SDAIN from SDAOUT and isolates SCLIN from
SCLOUT. Drive ENABLE all the way to V
CC
for normal
operation. Connect ENABLE to V
CC
if this feature is not
being used. For the LTC4300A-2, this is the supply voltage
for the devices on the card I
2
C busses. Connect pull-up
resistors from SDAOUT and SCLOUT to this pin. Place a
bypass capacitor of at least 0.01μF close to this pin for
best results.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the SCL bus on the card.
SCLIN (Pin 3): Serial Clock Input. Connect this pin to the
SCL bus on the backplane.
GND (Pin 4): Ground. Connect this pin to a ground plane
for best results.
READY/ACC (Pin 5): Connection Flag/Rise-Time Accelera-
tor Control. For the LTC4300A-1, this is an open-drain
NMOS output which pulls low when either ENABLE is
low or the start-up sequence described in the Operation
section has not been completed. READY goes high when
ENABLE is high and start-up is complete. Connect a 10k
resistor from this pin to V
CC
to provide the pull up. For
the LTC4300A-2, this is a CMOS threshold digital input
pin that enables and disables the rise-time accelerators
on all four SDA and SCL pins. Drive ACC all the way to the
V
CC2
supply voltage to enable all four accelerators; drive
ACC to ground to turn them off.
SDAIN (Pin 6): Serial Data Input. Connect this pin to the
SDA bus on the backplane.
SDAOUT (Pin 7): Serial Data Output. Connect this pin to
the SDA bus on the card.
V
CC
(Pin 8): Main Input Power Supply from Backplane.
This is the supply voltage for the devices on the back-
plane I
2
C busses. Connect pull-up resistors from SDAIN
and SCLIN (and also from SDAOUT and SCLOUT for the
LTC4300A-1) to this pin. Place a bypass capacitor of at
least 0.01μF close to this pin for best results.
LTC4300A-1/LTC4300A-2
6
4300a12fa
BLOCK DIAGRAM
2-Wire Bus Buffer and Hot Swap™ Controller
(LTC4300A-1)
100k
RCH1
100k
RCH3
–
+
5
–
+
0.5pF
READY
1ENABLE
UVLO
3SCLIN
4300A1 BD
CONNECT
STOP BIT AND BUS IDLE
4
4
GND
CONNECT
20pF
RD
S
QB
0.5μA
0.55V
CC
/
0.45V
CC
–
+
–
+
V
CC
– 1V
2mA
95μs
DELAY,
RISING
ONLY
BACKPLANE-TO-CARD
CONNECTION
CONNECTCONNECT
2 SCLOUT
6SDAIN
BACKPLANE-TO-CARD
CONNECTION
CONNECT
CONNECT
7 SDAOUT
8V
CC
1V
PRECHARGE
100k
RCH2
100k
RCH4
SLEW RATE
DETECTOR
2mA
SLEW RATE
DETECTOR
2mA
SLEW RATE
DETECTOR
2mA
SLEW RATE
DETECTOR
CONNECT
ENABLE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LTC4300A-2CMS8#PBF

Mfr. #:
Buy LTC4300A-2CMS8#PBF
Manufacturer:
Analog Devices Inc.
Description:
Interface - Signal Buffers, Repeaters 2-Wire Bus Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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