AT49BV8192AT-11TI Datasheet AT49BV8192A-11CI, AT49BV8192A-90TC, AT49BV8192AT-11CI | P1-P3

Features

• Single-voltage Read/Write Operation: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)

• Fast Read Access Time – 90 ns

• Internal Erase/Program Control

• Sector Architecture

– One 8K Word (16K Bytes) Boot Block with Programming Lockout

– Two 4K Word (8K Bytes) Parameter Blocks

– One 496K Word (992K Bytes) Main Memory Array Block

• Fast Sector Erase Time – 10 seconds

• Byte-by-byte or Word-by-word Programming – 30 µs Typical

• Hardware Data Protection

• Data Polling for End of Program Detection

• Low Power Dissipation

– 25 mA Active Current

– 50 µA CMOS Standby Current

• Typical 10,000 Write Cycles

Description

The AT49BV008A(T) and AT49BV8192A(T) are 3-volt, 8-megabit Flash memories

organized as 1,048,576 words of 8 bits each or 512K words of 16 bits each. Manufac-

tured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access

times to 90 ns with power dissipation of just 67 mW at 2.7V read. When deselected,

the CMOS standby current is less than 50 µA.

The device contains a user-enabled “boot block” protection feature. Two versions of

the feature are available: the AT49BV008A/8192A locates the boot block at lowest

order addresses (“bottom boot”); the AT49BV008AT/8192AT locates it at highest

order addresses (“top boot”).

To allow for simple in-system reprogrammability, the AT49BV008A(T)/8192A(T) does

not require high input voltages for programming. Reading data out of the device is

similar to reading from an EPROM; it has standard CE

, OE and WE inputs to avoid

8-megabit

(1M x 8/

512K x 16)

Flash Memory

AT49BV008A

AT49BV008AT

AT49BV8192A

AT49BV8192AT

AT49LV8192A

Rev. 1049I–03/01

Pin Configurations

Pin Name Function

A0 - A18 Addresses

Chip Enable

Output Enable

WE Write Enable

RESET

Reset

RDY/BUSY

Ready/Busy Output

VPP VPP can be left unconnected or

connected to VCC, GND, 5V or 12V.

The input has no effect on the

operation of the device.

I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1)

I/O15 (Data Input/Output, Word Mode)

A-1 (LSB Address Input, Byte Mode)

BYTE

Selects Byte or Word Mode

NC No Connect

(continued)

AT49BV008A(T)/8192A(T)

bus contention. Reprogramming the AT49BV008A(T)/

8192A(T) is performed by first erasing a block of data and

then by programming on a byte-by-byte or word-by-word

basis.

The device is erased by executing the Erase command

sequence; the device internally controls the erase opera-

tion. The memory is divided into four blocks for erase oper-

ations. There are two 4K word parameter block sections,

the boot block, and the main memory array block. The typi-

cal number of program and erase cycles is in excess of

10,000 cycles.

The optional 8K word boot block section includes a repro-

gramming lock out feature to provide data integrity. This

feature is enabled by a command sequence. Once the boot

block programming lockout feature is enabled, the data in

the boot block cannot be changed when input levels of 5.5

volts or less are used. The boot sector is designed to con-

tain user secure code.

For the AT49BV8192A(T), the BYTE

pin controls whether

the device data I/O pins operate in the byte or word config-

uration. If the BYTE

pin is set at a logic “1” or left open, the

device is in word configuration, I/O0 - I/O15 are active and

controlled by CE

and OE.

If the BYTE

pin is set at logic “0”, the device is in byte con-

figuration, and only data I/O pins I/O0 - I/O7 are active and

controlled by CE

and OE. The data I/O pins I/O8 - I/O14

are tri-stated and the I/O15 pin is used as an input for the

LSB (A-1) address function.

AT49BV8192A(T) TSOP Top View

Type 1

A15

A14

A13

A12

A11

A10

RESET

VPP

A18

A17

A16

BYTE

GND

I/O15 / A-1

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

GND

AT49BV008A(T) TSOP Top View

Type 1

A16

A15

A14

A13

A12

A11

RESET

VPP

RDY/BUSY

A18

A17

GND

A-1

A10

I/O7

I/O6

I/O5

I/O4

VCC

I/O3

I/O2

I/O1

I/O0

GND

AT49BV8192A(T)

CBGA Top View (Ball Down)

234567

A13

A14

A15

A16

BYTE

GND

A11

A10

A12

I/O14

I/O15

I/O7

I/O5

I/O6

I/O13

VPP

RST

I/O11

I/O12

I/O4

A18

I/O2

I/O3

VCC

A17

I/O8

I/O9

I/O10

I/O0

I/O1

GND

AT49BV008A(T) Standard Pin Definition

CBGA Top View (Ball Down)

234567

A13

A14

A15

A16

GND

A11

A10

A12

A-1

I/O7

I/O5

I/O6

VPP

RST

I/O4

A18

I/O2

I/O3

VCC

A17

I/O0

I/O1

GND

AT49BV008A(T) Alternate Pin Definition

CBGA Top View (Ball Down)

234567

A14

A15

A16

A17

GND

A12

A10

A13

A11

I/O7

I/O5

I/O6

VPP

RST

I/O4

A19

I/O2

I/O3

VCC

A18

I/O0

I/O1

GND

AT49BV8192A(T) SOIC (SOP) Top View

VPP

A18

A17

GND

I/O0

I/O8

I/O1

I/O9

I/O2

I/O10

I/O3

I/O11

RESET

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

Note: “•” denotes a white dot on the package.

AT49BV008A(T)/8192A(T)

AT49BV008A(T) Block Diagram

AT49BV8192A(T) Block Diagram

Device Operation

READ: The AT49BV008A(T)/8192A(T) is accessed like an

EPROM. When CE

and OE are low and WE is high, the

data stored at the memory location determined by the

address pins is asserted on the outputs. The outputs are

put in the high-impedance state whenever CE

or OE is

high. This dual-line control gives designers flexibility in pre-

venting bus contention.

COMMAND SEQUENCES: When the device is first pow-

ered on it will be reset to the read or standby mode

depending upon the state of the control line inputs. In order

to perform other device functions, a series of command

sequences are entered into the device. The command

sequences are shown in the Command Definitions table

(I/O8 - I/O15 are don’t care inputs for the command codes).

The command sequences are written by applying a low

pulse on the WE

or CE input with CE or WE low (respec-

tively) and OE

high. The address is latched on the falling

edge of CE

or WE, whichever occurs last. The data is

latched by the first rising edge of CE

or WE. Standard

microprocessor write timings are used. The address loca-

tions used in the command sequences are not affected by

entering the command sequences.

VPP

VCC

GND

CONTROL

LOGIC

DATA INPUTS/OUTPUTS

I/O0 - I/O7

DATA INPUTS/OUTPUTS

I/O0 - I/O7

RESET

ADDRESS

INPUTS

Y DECODER

INPUT/OUTPUT

BUFFERS

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

PROGRAM DATA

LATCHES

Y-GATING

AT49BV008A AT49BV008AT

Y-GATING

FFFFF FFFFF

MAIN MEMORY

(992K BYTES)

BOOT BLOCK

16K BYTES

PARAMETER

BLOCK 2

8K BYTES

PARAMETER

BLOCK 1

8K BYTES

PARAMETER

BLOCK 1

8K BYTES

PARAMETER

BLOCK 2

8K BYTES

BOOT BLOCK

16K BYTES

MAIN MEMORY

(992K BYTES)

08000

07FFF

FC000

FBFFF

06000

05FFF

FA000

F9FFF

X DECODER

04000

03FFF

F8000

F7FFF

00000 00000

VPP

VCC

GND

CONTROL

LOGIC

DATA INPUTS/OUTPUTS

I/O0 - I/O15

DATA INPUTS/OUTPUTS

I/O0 - I/O15

RESET

ADDRESS

INPUTS

Y DECODER

INPUT/OUTPUT

BUFFERS

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

PROGRAM DATA

LATCHES

Y-GATING

AT49BV8192A AT49BV8192AT

Y-GATING

7FFFF 7FFFF

MAIN MEMORY

(496K WORDS)

BOOT BLOCK

8K WORDS

PARAMETER

BLOCK 2

4K WORDS

PARAMETER

BLOCK 1

4K WORDS

PARAMETER

BLOCK 1

4K WORDS

PARAMETER

BLOCK 2

4K WORDS

BOOT BLOCK

8K WORDS

MAIN MEMORY

(496K WORDS)

04000

03FFF

7E000

7DFFF

03000

02FFF

7D000

7CFFF

X DECODER

02000

01FFF

7C000

7BFFF

00000 00000

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

AT49BV8192AT-11TI

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AT49BV8192AT-11TI

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