OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MAX1932ETC+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
MAX1932
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
EVALUATION KIT AVAILABLE
General Description
The MAX1932 generates a low-noise, high-voltage output
to bias avalanche photodiodes (APDs) in optical
receivers. Very low output ripple and noise is achieved by
a constant-frequency, pulse-width modulated (PWM)
boost topology combined with a unique architecture that
maintains regulation with an optional RC or LC post filter
inside its feedback loop. A precision reference and error
amplifier maintain 0.5% output voltage accuracy.
The MAX1932 protects expensive APDs against adverse
operating conditions while providing optimal bias.
Traditional boost converters measure switch current for
protection, whereas the MAX1932 integrates accurate
high-side current limiting to protect APDs under
avalanche conditions. A current-limit flag allows easy cali-
bration of the APD operating point by indicating the pre-
cise point of avalanche breakdown. The MAX1932 control
scheme prevents output overshoot and undershoot to
provide safe APD operation without data loss.
The output voltage can be accurately set with either
external resistors, an internal 8-bit DAC, an external
DAC, or other voltage source. Output span and offset
are independently settable with external resistors. This
optimizes the utilization of DAC resolution for applica-
tions that may require limited output voltage range, such
as 4.5V to 15V, 4.5V to 45V, 20V to 60V, or 40V to 90V.
Applications
Optical Receivers and Modules
Fiber Optic Network Equipment
Telecom Equipment
Laser Range Finders
PIN Diode Bias Supply
Benefits and Features
• Unique Architecture Delivers Excellent Accuracy for
Improved System Performance
• 0.5% Accurate Output
• Low Ripple Output (< 1mV)
• Protection Features Guarantee Safe Operation
• Accurate High-Side Current Limit
• Avalanche Indicator Flag
• Output-Voltage Flexibility Facilitates Multiple
Applications and Design Approaches
• 4.5V to 90V Output
• Set Output Voltage via 8-Bit SPI-Compatible
Internal DAC, External DAC, or External Resistors
• Small Circuit Footprint Reduces Equipment Size
• 12-Pin, 4mm x 4mm Thin QFN Package
• Circuit Height < 2mm
• Commonly Available 2.7V to 5.5V Input Voltage
Range
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX1932ETC -40°C to +85°C 12 Thin QFN
MAX1932
INPUT
2.7V TO 5.5V
APD BIAS OUTPUT
4.5V TO 90V
DAC INPUTS
AVALANCHE
INDICATOR
FLAG
VIN
COMP
SCLK
GND
FB
CS-
CS+
GATE
DACOUT
DIN
CS
CL
Typical Application Circuit
MAX1932
12
1
2
3
9
8
7
11 10
4 5 6
SCLK GND
COMP
FB
CS+
CS-
DACOUT GATE
VIN
DIN
CL
CS
Pin Configuration
19-2555; Rev 2; 5/15
MAX1932
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 2www.maximintegrated.com
Absolute Maximum Ratings
Electrical Characteristics
(V
IN
= 3.3V, CS = SCLK = D
IN
= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, T
A
= 0°C to +85°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VIN to GND...............................................................-0.3V to +6V
DIN, SCLK, CS, FB to GND ......................................-0.3V to +6V
COMP, DACOUT, GATE, CL to GND ...........-0.3V to (V
IN
+0.3V)
CS+, CS- to GND .................................................-0.3V to +110V
Continuous Power Dissipation (T
A
= +70°C)
12-Pin Thin QFN (derate 16.9mW/°C above +70°C) .1349mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL
Input Supply Range V
IN
2.7 5.5 V
V
IN
Undervoltage Lockout UVLO Both rise/fall, hysteresis = 100mV 2.1 2.6 V
Operating Supply Current I
IN
0.5 1 mA
V
IN
Shutdown Supply Current I
SHDN
00 hex loaded to DAC 25 65 µA
Input Resistance for CS+/CS- Resistance from either pin to ground 0.5 1 2.0 MΩ
Current-Limit Threshold
for CS+/CS-
1.80 2.00 2.20 V
Common-Mode Rejection
of Current Threshold
CS+ = 3V to 100V ±0.005 %/V
Gate-Driver Resistance Gate high or low, I
GATE
= ±50mA 5 10 Ω
FB Input Bias Current -25 +25 nA
T
A
= +25°C 1.24375 1.2500 1.25625
FB Voltage V
FB
T
A
= 0°C to +85°C 1.24250 1.2500 1.25750
V
FB Voltage
Temperature Coefficient
TCV
FB
0.0007 %/°C
FB to COMP Transconductance COMP = 1.5V 50 110 200 µS
COMP Pulldown Resistance
in Shutdown
DAC code = 00 hex 100 Ω
D AC OU T to FB V ol tag e D i ffer ence DAC code = FF hex -3 +3 mV
D AC OU T Differential Nonlinearity
(Note 1)
DAC Code = 01 to FF hex,
DAC guaranteed monotonic
-1 +1 LSB
D AC OU T Voltage Temperature
Coefficient
TCV
DACOUT
0.0007 %/°C
DACOUT Load Regulation
DAC code = 0F to FF hex, source or sink
50µA
-1 +1 mV
Switching Frequency f
OSC
250 300 340 kHz
GATE Maximum On-Time t
ON
3µs
MAX1932
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 3www.maximintegrated.com
Electrical Characteristics (continued)
(V
IN
= 3.3V, CS = SCLK = D
IN
= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, T
A
= 0°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (DIN, SCLK, CS)
Input Low Voltage 0.6 V
Input High Voltage 1.4 V
Input Hysteresis 200 mV
T
A
= +25°C -1 +1 µA
Input Leakage Current
T
A
= 0°C to +85°C 10 nA
Input Capacitance 5pF
DIGITAL OUTPUT (CL)
Output Low Voltage I
SINK
= 1mA 0.1 V
Output High Voltage I
SOURCE
= 0.5mA V
IN
- 0.5 V
SPI TIMING (FIGURE 5)
SCLK Clock Frequency f
SCLK
2 MHz
SCLK Low Period t
CL
125 ns
SCLK High Period t
CH
125 ns
Data Hold Time t
DH
0ns
Data Setup Time t
DS
125 ns
CS Assertion to SCLK
Rising Edge Setup Time
t
CSS0
200 ns
CS Deassertion to SCLK
Rising Edge Setup Time
t
CSS1
200 ns
SCLK Rising Edge
to CS Deassertion
t
CSH1
200 ns
SCLK Rising Edge
to CS Assertion
t
CSH0
200 ns
CS High Period t
CSW
300 ns
Electrical Characteristics
(V
IN
= 3.3V, CS = SCLK = D
IN
= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL
Input Supply Range V
IN
2.7 5.5 V
V
IN
Undervoltage Lockout UVLO Both rise/fall, hysteresis = 100mV 2.1 2.6 V
Operating Supply Current I
IN
1mA
V
IN
Shutdown Supply Current I
SHDN
00 hex loaded to DAC 65 µA
Input Resistance for CS+/CS- Resistance from either pin to ground 0.5 2 MΩ
Current-Limit Threshold
for CS+/CS-
1.80 2.20 V
Gate-Driver Resistance Gate high or low, I
GATE
= ±50mA 10 Ω
FB Input Bias Current -30 +30 nA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

MAX1932ETC+T

Mfr. #:
Buy MAX1932ETC+T
Manufacturer:
Maxim Integrated
Description:
Power Management Specialized - PMIC 0.5% Accurate APD Bias Supply
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet