1
PS8089D 05/24/06
12-Bit To 24-Bit Multiplexed D-Type Latch
with 3-State Outputs
Logic Block Diagram
G1
OE2B
C1
1D
1B1
TO 11 OTHER CHANNELS
OE1B
OEA
A1
LE1B
LE2B
LEA1B
LEA2B
SEL
1
1
C1
1D
C1
1D
C1
1D
2B1
23
6
28
8
1
29
56
55
30
27
2
Product Features
• PI74ALVCH16260 is designed for low voltage operation
• V
CC
= 2.3V to 3.6V
• Hysteresis on all inputs
• Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25°C
• Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25°C
• Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
PI74ALVCH16260
Product Description
The PI74ALVCH16260 is a 12-bit to 24-bit multiplexed D-type latch
designed for 2.3V to 3.6 V
CC
operation. It is used in applications
where two separate datapaths must be multiplexed onto, or
demultiplexed from, a single data path.
Typical applications include multiplexing and/or demultiplexing
address and data information in microprocessor or bus-interface
and in memory-interleaving.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available
for address and/or data transfer. The output-enable (OE1B, OE2B,
and OEA) inputs control bus transceiver functions. The OE1B and
OE2B control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal
storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B)
inputs are used to control data storage. When the latch-enable input
is HIGH, the latch is transparent. When the latch-enable input goes
LOW, the data present at the inputs is latched and remains latched
until the latch-enable input is returned HIGH.
To ensure high-impedance state during power up or power down,
OE should be tied to V
CC
through a pullup resistor whose minimum
value is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
